diff options
| author | Alec Roelke <ar4jc@virginia.edu> | 2017-06-14 17:33:29 -0400 |
|---|---|---|
| committer | Alec Roelke <ar4jc@virginia.edu> | 2017-07-11 03:45:14 +0000 |
| commit | 7e6a35374a944b67868d92ce85b427ea9103ca53 (patch) | |
| tree | 0fe3c97c11967468b2c66ce0edbc656d3c485a61 /src/arch/riscv/types.hh | |
| parent | 63d4005a29dea37e0219444a3de2cdb25289fdfb (diff) | |
| download | gem5-7e6a35374a944b67868d92ce85b427ea9103ca53.tar.xz | |
arch-riscv: Add support for compressed extension RV64C
This patch adds compatibility with the 64-bit compressed extension to
the RISC-V ISA, RV64C. Current versions of the toolchain may use
compressed instructions in glibc by default, which can only be
overridden by recompiling the entire toolchain (simply adding
"-march=rv64g" or "-march=rv64imafd" when compiling a binary is not
sufficient to use uncompressed instructions in glibc functions in the
binary).
[Update diassembly generation for new RegId type.]
[Rebase onto master.]
Change-Id: Ifd5a5ea746704ce7e1b111442c3eb84c509a98b4
Reviewed-on: https://gem5-review.googlesource.com/3860
Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Diffstat (limited to 'src/arch/riscv/types.hh')
| -rw-r--r-- | src/arch/riscv/types.hh | 32 |
1 files changed, 28 insertions, 4 deletions
diff --git a/src/arch/riscv/types.hh b/src/arch/riscv/types.hh index 976a9e70e..f17d0b235 100644 --- a/src/arch/riscv/types.hh +++ b/src/arch/riscv/types.hh @@ -12,7 +12,7 @@ * unmodified and in its entirety in all distributions of the software, * modified or unmodified, in source code or in binary form. * - * Copyright (c) 2016 The University of Virginia + * Copyright (c) 2017 The University of Virginia * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -50,11 +50,35 @@ namespace RiscvISA { + typedef uint32_t MachInst; typedef uint64_t ExtMachInst; -typedef GenericISA::UPCState<MachInst> PCState; -} +class PCState : public GenericISA::UPCState<MachInst> +{ + private: + bool _compressed; + + public: + PCState() : UPCState() { _compressed = false; } + PCState(Addr val) : UPCState(val) { _compressed = false; } + void compressed(bool c) { _compressed = c; } + bool compressed() { return _compressed; } + + bool + branching() const + { + if (_compressed) { + return npc() != pc() + sizeof(MachInst)/2 || + nupc() != upc() + 1; + } else { + return npc() != pc() + sizeof(MachInst) || + nupc() != upc() + 1; + } + } +}; + +} -#endif // __ARCH_RISCV_TYPES_HH__ +#endif // __ARCH_RISCV_TYPES_HH__
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