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| author | Robert <robert.scheffel1@tu-dresden.de> | 2018-03-13 14:29:00 +0100 |
|---|---|---|
| committer | Robert Scheffel <robert.scheffel1@tu-dresden.de> | 2018-07-09 11:17:11 +0000 |
| commit | 5de8ca95506a5f15bfbfdd2ca9babd282a882d1f (patch) | |
| tree | 1bc429aa1896dea5167e37000428d157b1a0b710 /src/arch/riscv/utility.hh | |
| parent | 98cbcbb54f56475759fae747b60e47568617640f (diff) | |
| download | gem5-5de8ca95506a5f15bfbfdd2ca9babd282a882d1f.tar.xz | |
arch-riscv: enable rudimentary fs simulation
These changes enable a simple binary to be simulated in full system mode.
Additionally, a new fault was implemented.
It is executed once the CPU is initialized.
This fault clears all interrupts and sets the pc to a reset vector.
Change-Id: I50cfac91a61ba39a6ef3d38caca8794073887c88
Reviewed-on: https://gem5-review.googlesource.com/9061
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/arch/riscv/utility.hh')
| -rw-r--r-- | src/arch/riscv/utility.hh | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/src/arch/riscv/utility.hh b/src/arch/riscv/utility.hh index 78e9b91a9..6c0fcc130 100644 --- a/src/arch/riscv/utility.hh +++ b/src/arch/riscv/utility.hh @@ -1,6 +1,7 @@ /* * Copyright (c) 2013 ARM Limited * Copyright (c) 2014-2015 Sven Karlsson + * Copyright (c) 2018 TU Dresden * All rights reserved * * The license below extends only to copyright in the software and shall @@ -41,6 +42,7 @@ * Authors: Andreas Hansson * Sven Karlsson * Alec Roelke + * Robert Scheffel */ #ifndef __ARCH_RISCV_UTILITY_HH__ @@ -117,6 +119,7 @@ getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp) inline void startupCPU(ThreadContext *tc, int cpuId) { + tc->activate(); } inline void @@ -183,11 +186,10 @@ getExecutingAsid(ThreadContext *tc) return 0; } -inline void -initCPU(ThreadContext *, int cpuId) -{ - panic("initCPU not implemented for Riscv.\n"); -} +/** + * init Cpu function + */ +void initCPU(ThreadContext *tc, int cpuId); } // namespace RiscvISA |