riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD

Third of five patches adding RISC-V to GEM5. This patch adds the RV64FD
extensions, which include single- and double-precision floating point
instructions.

Patch 1 introduced RISC-V and implemented the base instruction set, RV64I
and patch 2 implemented the integer multiply extension, RV64M.

Patch 4 will implement the atomic memory instructions, RV64A, and patch
5 will add support for timing, minor, and detailed CPU models that is
missing from the first four patches.

[Fixed exception handling in floating-point instructions to conform better
to IEEE-754 2008 standard and behavior of the Chisel-generated RISC-V
simulator.]
[Fixed style errors in decoder.isa.]
[Fixed some fuzz caused by modifying a previous patch.]
Signed-off by: Alec Roelke

Signed-off by: Jason Lowe-Power <jason@lowepower.com>

1 files changed, 40 insertions, 0 deletions

diff --git a/src/arch/riscv/utility.hh b/src/arch/riscv/utility.hh
index 56aa65f12..fc67fc806 100644
--- a/src/arch/riscv/utility.hh
+++ b/src/arch/riscv/utility.hh
@@ -56,6 +56,46 @@
 namespace RiscvISA
 {
 
+template<typename T> inline bool
+isquietnan(T val)
+{
+    return false;
+}
+
+template<> inline bool
+isquietnan<float>(float val)
+{
+    return std::isnan(val)
+        && (reinterpret_cast<uint32_t&>(val)&0x00400000);
+}
+
+template<> inline bool
+isquietnan<double>(double val)
+{
+    return std::isnan(val)
+        && (reinterpret_cast<uint64_t&>(val)&0x0008000000000000ULL);
+}
+
+template<typename T> inline bool
+issignalingnan(T val)
+{
+    return false;
+}
+
+template<> inline bool
+issignalingnan<float>(float val)
+{
+    return std::isnan(val)
+        && (reinterpret_cast<uint32_t&>(val)&0x00200000);
+}
+
+template<> inline bool
+issignalingnan<double>(double val)
+{
+    return std::isnan(val)
+        && (reinterpret_cast<uint64_t&>(val)&0x0004000000000000ULL);
+}
+
 inline PCState
 buildRetPC(const PCState &curPC, const PCState &callPC)
 {