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| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2019-01-09 14:50:27 +0000 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2019-01-10 17:55:42 +0000 |
| commit | 0a36956261c67d61def90e1aefeb6c46568ff167 (patch) | |
| tree | 5f6d72f83185698d45e1f4b3eba1537f1c370167 /src/arch/riscv | |
| parent | 13daa2e0620e71a1c11f94d1f8a864f73a52b94d (diff) | |
| download | gem5-0a36956261c67d61def90e1aefeb6c46568ff167.tar.xz | |
sim-se: Refactor clone to avoid most ifdefs
Some parts of clone are architecture dependent. In some cases, we are
able to use architecture-specific helper functions or register
aliases. However, there is still some architecture-specific that is
protected by ifdefs in the common clone implementation.
Move these architecture-specific bits to the architecture-specific OS
class instead to avoid these ifdefs and make the code a bit more
readable.
Change-Id: Ia0903d738d0ba890863bddfa77e3b717db7f45de
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Cc: Giacomo Travaglini <giacomo.travaglini@arm.com>
Cc: Javier Setoain <javier.setoain@arm.com>
Cc: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15435
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Diffstat (limited to 'src/arch/riscv')
| -rw-r--r-- | src/arch/riscv/linux/linux.hh | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/arch/riscv/linux/linux.hh b/src/arch/riscv/linux/linux.hh index cfc1d4fd7..2dac1fe32 100644 --- a/src/arch/riscv/linux/linux.hh +++ b/src/arch/riscv/linux/linux.hh @@ -31,6 +31,7 @@ #ifndef __ARCH_RISCV_LINUX_LINUX_HH__ #define __ARCH_RISCV_LINUX_LINUX_HH__ +#include "arch/riscv/utility.hh" #include "kern/linux/linux.hh" class RiscvLinux : public Linux @@ -187,6 +188,17 @@ class RiscvLinux : public Linux uint64_t freehigh; uint32_t mem_unit; } tgt_sysinfo; + + static void + archClone(uint64_t flags, + Process *pp, Process *cp, + ThreadContext *ptc, ThreadContext *ctc, + uint64_t stack, uint64_t tls) + { + RiscvISA::copyRegs(ptc, ctc); + if (stack) + ctc->setIntReg(RiscvISA::StackPointerReg, stack); + } }; #endif |