syscall_emul: expand AuxVector class

The AuxVector class is responsible for holding Process data.
The data that it holds is normally setup by an OS kernel in
the process address space. The purpose behind doing this is
to pass in information that the process will need for various
reasons. (Check out the enum in the header file for an idea of
what the AuxVector holds.)

The AuxVector struct was changed into a class and encapsulation
methods were added to protect access to the member variables.

The host ISA may have a different endianness than the simulated
ISA. Since data is passed between the process address space and
the simulator for auxiliary vectors, we need to worry about
maintaining endianness for the right context.

Change-Id: I32c5ac4b679559886e1efeb4b5483b92dfc94af9
Reviewed-on: https://gem5-review.googlesource.com/12109
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

1 files changed, 4 insertions, 4 deletions

diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index 4afc72147..4e97fcf42 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -205,11 +205,11 @@ RiscvProcess::argsInit(int pageSize)
     };
     for (const AuxVector<IntType>& aux: auxv) {
         DPRINTF(Stack, "Wrote aux key %s to address %p\n",
-                aux_keys[aux.a_type], (void*)sp);
-        pushOntoStack((uint8_t*)&aux.a_type, sizeof(IntType));
+                aux_keys[aux.getAuxType()], (void*)sp);
+        pushOntoStack((uint8_t*)&aux.getAuxType(), sizeof(IntType));
         DPRINTF(Stack, "Wrote aux value %x to address %p\n",
-                aux.a_val, (void*)sp);
-        pushOntoStack((uint8_t*)&aux.a_val, sizeof(IntType));
+                aux.getAuxVal(), (void*)sp);
+        pushOntoStack((uint8_t*)&aux.getAuxVal(), sizeof(IntType));
     }
 
     ThreadContext *tc = system->getThreadContext(contextIds[0]);