diff options
author | Brandon Potter <brandon.potter@amd.com> | 2016-11-09 14:27:40 -0600 |
---|---|---|
committer | Brandon Potter <brandon.potter@amd.com> | 2016-11-09 14:27:40 -0600 |
commit | 3886c4a8f2e1bfe17cbf7a5a76ba0fc978c6bb48 (patch) | |
tree | 5a1ce6cbf42009fc9199c7ecfb068890ca74dbd4 /src/arch/riscv | |
parent | 7b6cf951e2f0fa70d6599f1e1d03f664b674a75e (diff) | |
download | gem5-3886c4a8f2e1bfe17cbf7a5a76ba0fc978c6bb48.tar.xz |
syscall_emul: [patch 5/22] remove LiveProcess class and use Process instead
The EIOProcess class was removed recently and it was the only other class
which derived from Process. Since every Process invocation is also a
LiveProcess invocation, it makes sense to simplify the organization by
combining the fields from LiveProcess into Process.
Diffstat (limited to 'src/arch/riscv')
-rw-r--r-- | src/arch/riscv/linux/process.cc | 6 | ||||
-rw-r--r-- | src/arch/riscv/linux/process.hh | 4 | ||||
-rw-r--r-- | src/arch/riscv/process.cc | 16 | ||||
-rw-r--r-- | src/arch/riscv/process.hh | 7 |
4 files changed, 16 insertions, 17 deletions
diff --git a/src/arch/riscv/linux/process.cc b/src/arch/riscv/linux/process.cc index c6c61c751..24ea056cd 100644 --- a/src/arch/riscv/linux/process.cc +++ b/src/arch/riscv/linux/process.cc @@ -53,7 +53,7 @@ using namespace RiscvISA; /// Target uname() handler. static SyscallReturn -unameFunc(SyscallDesc *desc, int callnum, LiveProcess *process, +unameFunc(SyscallDesc *desc, int callnum, Process *process, ThreadContext *tc) { int index = 0; @@ -126,8 +126,8 @@ std::map<int, SyscallDesc> RiscvLinuxProcess::syscallDescs = { {2011, SyscallDesc("getmainvars", unimplementedFunc)}, }; -RiscvLinuxProcess::RiscvLinuxProcess(LiveProcessParams * params, - ObjectFile *objFile) : RiscvLiveProcess(params, objFile) +RiscvLinuxProcess::RiscvLinuxProcess(ProcessParams * params, + ObjectFile *objFile) : RiscvProcess(params, objFile) {} SyscallDesc* diff --git a/src/arch/riscv/linux/process.hh b/src/arch/riscv/linux/process.hh index 5edc0e149..f83037fd4 100644 --- a/src/arch/riscv/linux/process.hh +++ b/src/arch/riscv/linux/process.hh @@ -41,11 +41,11 @@ #include "sim/eventq.hh" /// A process with emulated Riscv/Linux syscalls. -class RiscvLinuxProcess : public RiscvLiveProcess +class RiscvLinuxProcess : public RiscvProcess { public: /// Constructor. - RiscvLinuxProcess(LiveProcessParams * params, ObjectFile *objFile); + RiscvLinuxProcess(ProcessParams * params, ObjectFile *objFile); virtual SyscallDesc* getDesc(int callnum); diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc index 4eb3159af..8629a57d6 100644 --- a/src/arch/riscv/process.cc +++ b/src/arch/riscv/process.cc @@ -50,8 +50,8 @@ using namespace std; using namespace RiscvISA; -RiscvLiveProcess::RiscvLiveProcess(LiveProcessParams * params, - ObjectFile *objFile) : LiveProcess(params, objFile) +RiscvProcess::RiscvProcess(ProcessParams * params, + ObjectFile *objFile) : Process(params, objFile) { // Set up stack. On RISC-V, stack starts at the top of kuseg // user address space. RISC-V stack grows down from here @@ -68,15 +68,15 @@ RiscvLiveProcess::RiscvLiveProcess(LiveProcessParams * params, } void -RiscvLiveProcess::initState() +RiscvProcess::initState() { - LiveProcess::initState(); + Process::initState(); argsInit<uint64_t>(PageBytes); } template<class IntType> void -RiscvLiveProcess::argsInit(int pageSize) +RiscvProcess::argsInit(int pageSize) { updateBias(); @@ -215,7 +215,7 @@ RiscvLiveProcess::argsInit(int pageSize) } RiscvISA::IntReg -RiscvLiveProcess::getSyscallArg(ThreadContext *tc, int &i) +RiscvProcess::getSyscallArg(ThreadContext *tc, int &i) { // RISC-V only has four system call argument registers by convention, so // if a larger index is requested return 0 @@ -227,13 +227,13 @@ RiscvLiveProcess::getSyscallArg(ThreadContext *tc, int &i) } void -RiscvLiveProcess::setSyscallArg(ThreadContext *tc, int i, RiscvISA::IntReg val) +RiscvProcess::setSyscallArg(ThreadContext *tc, int i, RiscvISA::IntReg val) { tc->setIntReg(SyscallArgumentRegs[i], val); } void -RiscvLiveProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret) +RiscvProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret) { if (sysret.successful()) { // no error diff --git a/src/arch/riscv/process.hh b/src/arch/riscv/process.hh index 53aa7c00a..8275a118a 100644 --- a/src/arch/riscv/process.hh +++ b/src/arch/riscv/process.hh @@ -38,14 +38,13 @@ #include "mem/page_table.hh" #include "sim/process.hh" -class LiveProcess; class ObjectFile; class System; -class RiscvLiveProcess : public LiveProcess +class RiscvProcess : public Process { protected: - RiscvLiveProcess(LiveProcessParams * params, ObjectFile *objFile); + RiscvProcess(ProcessParams * params, ObjectFile *objFile); void initState(); @@ -55,7 +54,7 @@ class RiscvLiveProcess : public LiveProcess public: RiscvISA::IntReg getSyscallArg(ThreadContext *tc, int &i); /// Explicitly import the otherwise hidden getSyscallArg - using LiveProcess::getSyscallArg; + using Process::getSyscallArg; void setSyscallArg(ThreadContext *tc, int i, RiscvISA::IntReg val); void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value); }; |