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| author | Gabe Black <gabeblack@google.com> | 2018-01-12 16:16:56 -0800 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2018-01-16 10:17:23 +0000 |
| commit | 694672093ece3253c984d8809f64440022a82978 (patch) | |
| tree | 0e9d98868ce45c6392e6d70f2e8aa19beba3bf8d /src/arch/riscv | |
| parent | b8b13206c8d45cdcc16157d137845706bae915dd (diff) | |
| download | gem5-694672093ece3253c984d8809f64440022a82978.tar.xz | |
sim: Simplify registerThreadContext a little bit.
The code in this function was a little convoluted. This change attempts
to simplify it a little bit to make it easier to read.
Change-Id: I1ae557b9fede47fa89a9ea550bd0af8ad242449f
Reviewed-on: https://gem5-review.googlesource.com/7421
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/riscv')
0 files changed, 0 insertions, 0 deletions