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| author | Gabe Black <gabeblack@google.com> | 2018-10-12 17:21:18 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2018-11-05 23:42:08 +0000 |
| commit | 9dbc9bb4f2b49cfa0d9f1cf844929896c27a2d27 (patch) | |
| tree | 03850d679495f2edab2b334e76674d82ec43e8d1 /src/arch/riscv | |
| parent | 543b7865337a982dc1f49cc5dfeee960da20b329 (diff) | |
| download | gem5-9dbc9bb4f2b49cfa0d9f1cf844929896c27a2d27.tar.xz | |
base: Add standard types for floating and nonfloating point register values.
These should be used instead of the ISA specific ones, and should be
at least as large as the largest primitive register type in all the
ISAs.
Change-Id: Iaac104eef74eabcdd87787b1cdf8bea22d449eda
Reviewed-on: https://gem5-review.googlesource.com/c/13615
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/arch/riscv')
0 files changed, 0 insertions, 0 deletions