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author | Alec Roelke <ar4jc@virginia.edu> | 2017-07-13 16:26:53 -0400 |
---|---|---|
committer | Alec Roelke <ar4jc@virginia.edu> | 2017-07-14 20:29:09 +0000 |
commit | d72eafa64b4313f30f4c7a25000ff04f5cf30380 (patch) | |
tree | b998acd6480a8186afce1bbbcfefb0c5df06216a /src/arch/riscv | |
parent | c473bdb8916528be4ff896c5e9378e6200f68939 (diff) | |
download | gem5-d72eafa64b4313f30f4c7a25000ff04f5cf30380.tar.xz |
riscv: Add unused attribute to some registers.hh constants
Three of the constants defined in arch/riscv/registers.hh
(ReturnValueReg, SyscallNumReg, and SyscallPseudoReturnReg) may cause
the compiler to warn that they are unused, which results in an error.
This patch adds M5_VAR_USED attributes to them to stop this.
Change-Id: Ie6389a55e8ffb3d003a47d02e76bdf9fb5219457
Reviewed-on: https://gem5-review.googlesource.com/4040
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Diffstat (limited to 'src/arch/riscv')
-rw-r--r-- | src/arch/riscv/registers.hh | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh index e2b04ab84..114d7e9e1 100644 --- a/src/arch/riscv/registers.hh +++ b/src/arch/riscv/registers.hh @@ -93,7 +93,7 @@ const int GlobalPointerReg = 3; const int ThreadPointerReg = 4; const int FramePointerReg = 8; const std::vector<int> ReturnValueRegs = {10, 11}; -const int ReturnValueReg = ReturnValueRegs[0]; +const int ReturnValueReg M5_VAR_USED = ReturnValueRegs[0]; const std::vector<int> ArgumentRegs = {10, 11, 12, 13, 14, 15, 16, 17}; const int AMOTempReg = 32; @@ -118,10 +118,10 @@ const std::vector<std::string> FloatRegNames = { "ft8", "ft9", "ft10", "ft11" }; -const int SyscallNumReg = ArgumentRegs[7]; +const int SyscallNumReg M5_VAR_USED = ArgumentRegs[7]; const std::vector<int> SyscallArgumentRegs = {ArgumentRegs[0], ArgumentRegs[1], ArgumentRegs[2], ArgumentRegs[3]}; -const int SyscallPseudoReturnReg = ReturnValueRegs[0]; +const int SyscallPseudoReturnReg M5_VAR_USED = ReturnValueRegs[0]; enum MiscRegIndex { MISCREG_USTATUS = 0x000, |