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| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2018-02-26 17:27:04 +0000 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2018-05-08 15:04:12 +0000 |
| commit | 05ee4c5b53cd0eaee5725abf039285156dab2734 (patch) | |
| tree | 6a003e868d24fc3aca53fe32bd2b48ff0febca1c /src/arch/riscv | |
| parent | 6d2e71156c00482447f2f33f65de072477ef64bd (diff) | |
| download | gem5-05ee4c5b53cd0eaee5725abf039285156dab2734.tar.xz | |
dev: Add support for a simple debug UART
Add a simple memory-mapped device that forwards writes to a serial
devices and treats reads as reads from the device. Unlike real UART
models, this one doesn't support interrupts.
This is useful to implement various debug devices that exist in many
systems.
Change-Id: I1e4300e4d3b70825a15d03f47d4e026941f9066c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10025
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Diffstat (limited to 'src/arch/riscv')
0 files changed, 0 insertions, 0 deletions