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| author | Sophiane Senni <sophiane.senni@gmail.com> | 2016-11-30 17:10:27 -0500 |
|---|---|---|
| committer | Sophiane Senni <sophiane.senni@gmail.com> | 2016-11-30 17:10:27 -0500 |
| commit | ce2722cdd97a31f85d36f6c32637b230e3c25c73 (patch) | |
| tree | 72993532267d3f1f99e8519be837dd7c523a722f /src/arch/riscv | |
| parent | 047caf24ba9a640247b63584c2291e760f1f4d54 (diff) | |
| download | gem5-ce2722cdd97a31f85d36f6c32637b230e3c25c73.tar.xz | |
mem: Split the hit_latency into tag_latency and data_latency
If the cache access mode is parallel, i.e. "sequential_access" parameter
is set to "False", tags and data are accessed in parallel. Therefore,
the hit_latency is the maximum latency between tag_latency and
data_latency. On the other hand, if the cache access mode is
sequential, i.e. "sequential_access" parameter is set to "True",
tags and data are accessed sequentially. Therefore, the hit_latency
is the sum of tag_latency plus data_latency.
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/arch/riscv')
0 files changed, 0 insertions, 0 deletions