misc: Rename misc.(hh|cc) to logging.(hh|cc)

These files aren't a collection of miscellaneous stuff, they're the
definition of the Logger interface, and a few utility macros for
calling into that interface (panic, warn, etc.).

Change-Id: I84267ac3f45896a83c0ef027f8f19c5e9a5667d1
Reviewed-on: https://gem5-review.googlesource.com/6226
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

7 files changed, 7 insertions, 7 deletions

diff --git a/src/arch/riscv/decoder.hh b/src/arch/riscv/decoder.hh
index c1d68bf06..91fe7873e 100644
--- a/src/arch/riscv/decoder.hh
+++ b/src/arch/riscv/decoder.hh
@@ -36,7 +36,7 @@
 #include "arch/generic/decode_cache.hh"
 #include "arch/riscv/isa_traits.hh"
 #include "arch/riscv/types.hh"
-#include "base/misc.hh"
+#include "base/logging.hh"
 #include "base/types.hh"
 #include "cpu/static_inst.hh"
 #include "debug/Decode.hh"
diff --git a/src/arch/riscv/interrupts.hh b/src/arch/riscv/interrupts.hh
index 36eb52909..cfb9a5b7e 100644
--- a/src/arch/riscv/interrupts.hh
+++ b/src/arch/riscv/interrupts.hh
@@ -31,7 +31,7 @@
 #ifndef __ARCH_RISCV_INTERRUPT_HH__
 #define __ARCH_RISCV_INTERRUPT_HH__
 
-#include "base/misc.hh"
+#include "base/logging.hh"
 #include "params/RiscvInterrupts.hh"
 #include "sim/sim_object.hh"
 
diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index 18dc1ba4c..4f8b4dc7a 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -43,7 +43,7 @@
 
 #include "arch/riscv/registers.hh"
 #include "arch/riscv/types.hh"
-#include "base/misc.hh"
+#include "base/logging.hh"
 #include "cpu/reg_class.hh"
 #include "sim/sim_object.hh"
 
diff --git a/src/arch/riscv/locked_mem.hh b/src/arch/riscv/locked_mem.hh
index f334385b1..61fbe0de1 100644
--- a/src/arch/riscv/locked_mem.hh
+++ b/src/arch/riscv/locked_mem.hh
@@ -51,7 +51,7 @@
 #include <stack>
 
 #include "arch/registers.hh"
-#include "base/misc.hh"
+#include "base/logging.hh"
 #include "base/trace.hh"
 #include "debug/LLSC.hh"
 #include "mem/packet.hh"
diff --git a/src/arch/riscv/pagetable.hh b/src/arch/riscv/pagetable.hh
index 72573cad6..249d03264 100644
--- a/src/arch/riscv/pagetable.hh
+++ b/src/arch/riscv/pagetable.hh
@@ -34,7 +34,7 @@
 #ifndef __ARCH_RISCV_PAGETABLE_H__
 #define __ARCH_RISCV_PAGETABLE_H__
 
-#include "base/misc.hh"
+#include "base/logging.hh"
 #include "base/types.hh"
 #include "sim/serialize.hh"
 
diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index eeea5ee48..54afc854c 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -43,7 +43,7 @@
 #include "arch/riscv/isa_traits.hh"
 #include "base/loader/elf_object.hh"
 #include "base/loader/object_file.hh"
-#include "base/misc.hh"
+#include "base/logging.hh"
 #include "cpu/thread_context.hh"
 #include "debug/Stack.hh"
 #include "mem/page_table.hh"
diff --git a/src/arch/riscv/pseudo_inst.hh b/src/arch/riscv/pseudo_inst.hh
index 646e978f8..49cceb86b 100644
--- a/src/arch/riscv/pseudo_inst.hh
+++ b/src/arch/riscv/pseudo_inst.hh
@@ -32,7 +32,7 @@
 #define __ARCH_RISCV_PSEUDO_INST_HH__
 
 #include "arch/generic/pseudo_inst.hh"
-#include "base/misc.hh"
+#include "base/logging.hh"
 
 class ThreadContext;