diff options
| author | Gabe Black <gabeblack@google.com> | 2018-10-18 17:34:08 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-01-22 21:15:45 +0000 |
| commit | 230b892fa3f484a46f4cd77f889f8793416b91e2 (patch) | |
| tree | 53b32ed7120d019399e36d04655487745bbba9ee /src/arch/riscv | |
| parent | 774770a6410abb129e2a19de1ca50d7c0c311fef (diff) | |
| download | gem5-230b892fa3f484a46f4cd77f889f8793416b91e2.tar.xz | |
arch: cpu: Stop passing around misc registers by reference.
These values are all basic integers (specifically uint64_t now), and
so passing them by const & is actually less efficient since there's a
extra level of indirection and an extra value, and the same sized value
(a 64 bit pointer vs. a 64 bit int) is being passed around.
Change-Id: Ie9956b8dc4c225068ab1afaba233ec2b42b76da3
Reviewed-on: https://gem5-review.googlesource.com/c/13626
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/arch/riscv')
| -rw-r--r-- | src/arch/riscv/isa.cc | 6 | ||||
| -rw-r--r-- | src/arch/riscv/isa.hh | 4 |
2 files changed, 5 insertions, 5 deletions
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc index d99a74220..0f184b882 100644 --- a/src/arch/riscv/isa.cc +++ b/src/arch/riscv/isa.cc @@ -164,7 +164,7 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc) } void -ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) +ISA::setMiscRegNoEffect(int misc_reg, MiscReg val) { if (misc_reg > NumMiscRegs || misc_reg < 0) { // Illegal CSR @@ -175,7 +175,7 @@ ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) } void -ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) +ISA::setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc) { if (misc_reg >= MISCREG_CYCLE && misc_reg <= MISCREG_HPMCOUNTER31) { // Ignore writes to HPM counters for now @@ -200,4 +200,4 @@ RiscvISA::ISA * RiscvISAParams::create() { return new RiscvISA::ISA(this); -}
\ No newline at end of file +} diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh index f96b07275..2602f6dde 100644 --- a/src/arch/riscv/isa.hh +++ b/src/arch/riscv/isa.hh @@ -76,8 +76,8 @@ class ISA : public SimObject MiscReg readMiscRegNoEffect(int misc_reg) const; MiscReg readMiscReg(int misc_reg, ThreadContext *tc); - void setMiscRegNoEffect(int misc_reg, const MiscReg &val); - void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc); + void setMiscRegNoEffect(int misc_reg, MiscReg val); + void setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc); RegId flattenRegId(const RegId ®Id) const { return regId; } int flattenIntIndex(int reg) const { return reg; } |