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authorGabe Black <gabeblack@google.com>2018-01-04 01:22:49 -0800
committerGabe Black <gabeblack@google.com>2018-01-19 20:20:57 +0000
commit372adea6879ac549df4a415b5913d28b6683d535 (patch)
tree2319ce7ae4f5cbdd381038cea4f7f9ce33d3c835 /src/arch/riscv
parentd76798c3e5611a9673bd1da9589a0081610cef5b (diff)
downloadgem5-372adea6879ac549df4a415b5913d28b6683d535.tar.xz
arch, mem, sim: Consolidate and rename the SE mode page table classes.
Now that Nothing inherits from PageTableBase directly, it can be merged into FuncPageTable. This change also takes the opportunity to rename the combined class to EmulationPageTable which lets you know that it's specifically for SE mode. Also remove the page table entry cache since it doesn't seem to actually improve performance. The TLBs likely absorb the majority of the locality, essentially acting like a cache like they would in real hardware. Change-Id: If1bcb91aed08686603bf7bee37298c0eee826e13 Reviewed-on: https://gem5-review.googlesource.com/7342 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/arch/riscv')
-rw-r--r--src/arch/riscv/process.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index 73df5f50d..b3e98aefb 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -60,8 +60,8 @@ using namespace std;
using namespace RiscvISA;
RiscvProcess::RiscvProcess(ProcessParams *params, ObjectFile *objFile) :
- Process(params, new FuncPageTable(params->name, params->pid,
- PageBytes),
+ Process(params,
+ new EmulationPageTable(params->name, params->pid, PageBytes),
objFile)
{
fatal_if(params->useArchPT, "Arch page tables not implemented.");