alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT.

This constant is, first, a #define, and second only used in one place.

In that one place, it appears that the code it guards is no longer
necessary in general. It was originally written to avoid refetching a
block of data that you're still in, even if you've moved slightly
farther in it because you're skipping the next instruction due to an
annulled branch delay slot. In reality however, in SPARC, the one ISA
I'm aware of which has this sort of branching behavior, the PC state
object will correctly determine that no branch is happening in these
cases. Code lower down in the loop will then recompute where fetching
should continue based on the next PC, automatically skipping the
annulled branch slot without misinterpretting the gap as a branch.

This change therefore also removes this block of code.

Change-Id: I820ebc9df10aeb4fcb69c12f6a784e9ec616743c
Reviewed-on: https://gem5-review.googlesource.com/6821
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

1 files changed, 0 insertions, 3 deletions

diff --git a/src/arch/riscv/isa_traits.hh b/src/arch/riscv/isa_traits.hh
index 21e684a25..abafad2e2 100644
--- a/src/arch/riscv/isa_traits.hh
+++ b/src/arch/riscv/isa_traits.hh
@@ -57,9 +57,6 @@ namespace RiscvISA
 
 using namespace LittleEndianGuest;
 
-// Riscv does NOT have a delay slot
-#define ISA_HAS_DELAY_SLOT 0
-
 const Addr PageShift = 12;
 const Addr PageBytes = ULL(1) << PageShift;