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authorRekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com>2017-04-05 13:14:34 -0500
committerAndreas Sandberg <andreas.sandberg@arm.com>2017-07-05 14:43:49 +0000
commita473b5a6eb269cc303ecfb5e5643d891a5d255d9 (patch)
tree4fde47e5c62c566f81d13f6e90ad98cca781ff6e /src/arch/riscv
parent43d833246fcfe092a0c08dde1fdf7e3d409d1af9 (diff)
downloadgem5-a473b5a6eb269cc303ecfb5e5643d891a5d255d9.tar.xz
cpu: Simplify the rename interface and use RegId
With the hierarchical RegId there are a lot of functions that are redundant now. The idea behind the simplification is that instead of having the regId, telling which kind of register read/write/rename/lookup/etc. and then the function panic_if'ing if the regId is not of the appropriate type, we provide an interface that decides what kind of register to read depending on the register type of the given regId. Change-Id: I7d52e9e21fc01205ae365d86921a4ceb67a57178 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2702
Diffstat (limited to 'src/arch/riscv')
-rw-r--r--src/arch/riscv/isa.hh7
-rw-r--r--src/arch/riscv/isa/base.isa13
-rw-r--r--src/arch/riscv/isa/formats/type.isa2
3 files changed, 14 insertions, 8 deletions
diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index d2f38b158..3f2412303 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -44,6 +44,7 @@
#include "arch/riscv/registers.hh"
#include "arch/riscv/types.hh"
#include "base/misc.hh"
+#include "cpu/reg_class.hh"
#include "sim/sim_object.hh"
struct RiscvISAParams;
@@ -78,6 +79,12 @@ class ISA : public SimObject
void
setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
+ RegId
+ flattenRegId(const RegId &regId) const
+ {
+ return regId;
+ }
+
int
flattenIntIndex(int reg) const
{
diff --git a/src/arch/riscv/isa/base.isa b/src/arch/riscv/isa/base.isa
index dafccc981..a7e2fc954 100644
--- a/src/arch/riscv/isa/base.isa
+++ b/src/arch/riscv/isa/base.isa
@@ -70,13 +70,12 @@ output decoder {{
std::string
RiscvStaticInst::regName(RegId reg) const
{
- switch (reg.regClass) {
- case IntRegClass:
- return std::string(RegisterNames[reg.regIdx]);
- case FloatRegClass:
- return std::string("f") + std::to_string(reg.regIdx);
- default:
- return csprintf("unknown[%i/%i]", reg.regClass, reg.regIdx);
+ if (reg.isIntReg()) {
+ return std::string(RegisterNames[reg.index()]);
+ } else if (reg.isFloatReg()) {
+ return std::string("f") + std::to_string(reg.index());
+ } else {
+ return csprintf("%s{%i}", reg.className(), reg.index());
}
}
}};
diff --git a/src/arch/riscv/isa/formats/type.isa b/src/arch/riscv/isa/formats/type.isa
index 0f2ffe9c4..f6a563699 100644
--- a/src/arch/riscv/isa/formats/type.isa
+++ b/src/arch/riscv/isa/formats/type.isa
@@ -210,7 +210,7 @@ output decoder {{
Jump::branchTarget(ThreadContext *tc) const
{
PCState pc = tc->pcState();
- IntReg Rs1 = tc->readIntReg(_srcRegIdx[0].regIdx);
+ IntReg Rs1 = tc->readIntReg(_srcRegIdx[0].index());
pc.set((Rs1 + imm)&~0x1);
return pc;
}