arch,sim: Merge initCPU into the ISA System classes.

Those classes are already ISA specific, so we can just move initCPU's
contents there and take it out of utility.hh, utility.cc, and the base
System's initState.

Change-Id: I28f0d0b50d83efe5116b0b24d20f8182a02823e7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24905
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

4 files changed, 6 insertions, 50 deletions

diff --git a/src/arch/riscv/SConscript b/src/arch/riscv/SConscript
index 2ddba722b..25adb53a3 100644
--- a/src/arch/riscv/SConscript
+++ b/src/arch/riscv/SConscript
@@ -57,7 +57,6 @@ if env['TARGET_ISA'] == 'riscv':
     Source('stacktrace.cc')
     Source('tlb.cc')
     Source('system.cc')
-    Source('utility.cc')
 
     Source('linux/process.cc')
     Source('linux/linux.cc')
diff --git a/src/arch/riscv/bare_metal/system.cc b/src/arch/riscv/bare_metal/system.cc
index 44e14e5ce..8d4ea414d 100644
--- a/src/arch/riscv/bare_metal/system.cc
+++ b/src/arch/riscv/bare_metal/system.cc
@@ -30,6 +30,7 @@
 
 #include "arch/riscv/bare_metal/system.hh"
 
+#include "arch/riscv/faults.hh"
 #include "base/loader/object_file.hh"
 
 BareMetalRiscvSystem::BareMetalRiscvSystem(Params *p)
@@ -54,6 +55,11 @@ BareMetalRiscvSystem::initState()
     // Call the initialisation of the super class
     RiscvSystem::initState();
 
+    for (auto *tc: threadContexts) {
+        RiscvISA::Reset().invoke(tc);
+        tc->activate();
+    }
+
     // load program sections into memory
     if (!bootloader->buildImage().write(physProxy)) {
         warn("could not load sections to memory");
diff --git a/src/arch/riscv/utility.cc b/src/arch/riscv/utility.cc
deleted file mode 100644
index 949d7c66f..000000000
--- a/src/arch/riscv/utility.cc
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright (c) 2018 TU Dresden
- * All rights reserved
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Robert Scheffel
- */
-
-#include "arch/riscv/utility.hh"
-
-#include "arch/riscv/faults.hh"
-
-namespace RiscvISA
-{
-
-void initCPU(ThreadContext *tc, int cpuId)
-{
-    Reset().invoke(tc);
-    tc->activate();
-}
-
-}
diff --git a/src/arch/riscv/utility.hh b/src/arch/riscv/utility.hh
index f6e1f348a..1b8e2d93b 100644
--- a/src/arch/riscv/utility.hh
+++ b/src/arch/riscv/utility.hh
@@ -181,11 +181,6 @@ getExecutingAsid(ThreadContext *tc)
     return 0;
 }
 
-/**
- * init Cpu function
- */
-void initCPU(ThreadContext *tc, int cpuId);
-
 } // namespace RiscvISA
 
 #endif // __ARCH_RISCV_UTILITY_HH__