diff options
| author | Gabe Black <gabeblack@google.com> | 2018-11-19 18:14:16 -0800 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-01-31 11:02:05 +0000 |
| commit | 5edfb67041ad1c246f4ceca147f06b9db3c0ecc3 (patch) | |
| tree | 22cc08624db8bfa11e4ea7c9817a864ebc2ea706 /src/arch/riscv | |
| parent | 25474167e5b247d1b91fbf802c5b396a63ae705e (diff) | |
| download | gem5-5edfb67041ad1c246f4ceca147f06b9db3c0ecc3.tar.xz | |
arch: cpu: Rename *FloatRegBits* to *FloatReg*.
Now that there's no plain FloatReg, there's no reason to distinguish
FloatRegBits with a special suffix since it's the only way to read or
write FP registers.
Change-Id: I3a60168c1d4302aed55223ea8e37b421f21efded
Reviewed-on: https://gem5-review.googlesource.com/c/14460
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/arch/riscv')
| -rw-r--r-- | src/arch/riscv/registers.hh | 2 | ||||
| -rw-r--r-- | src/arch/riscv/remote_gdb.cc | 4 | ||||
| -rw-r--r-- | src/arch/riscv/remote_gdb.hh | 2 |
3 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh index a67274221..7f7cefee9 100644 --- a/src/arch/riscv/registers.hh +++ b/src/arch/riscv/registers.hh @@ -65,7 +65,7 @@ using RiscvISAInst::MaxInstDestRegs; const int MaxMiscDestRegs = 1; typedef RegVal IntReg; -typedef RegVal FloatRegBits; +typedef RegVal FloatReg; typedef uint8_t CCReg; // Not applicable to Riscv typedef RegVal MiscReg; diff --git a/src/arch/riscv/remote_gdb.cc b/src/arch/riscv/remote_gdb.cc index 6d56a93b6..fe339ffc8 100644 --- a/src/arch/riscv/remote_gdb.cc +++ b/src/arch/riscv/remote_gdb.cc @@ -168,7 +168,7 @@ RemoteGDB::RiscvGdbRegCache::getRegs(ThreadContext *context) r.gpr[i] = context->readIntReg(i); r.pc = context->pcState().pc(); for (int i = 0; i < NumFloatRegs; i++) - r.fpr[i] = context->readFloatRegBits(i); + r.fpr[i] = context->readFloatReg(i); r.csr_base = context->readMiscReg(0); r.fflags = context->readMiscReg(CSR_FFLAGS); @@ -186,7 +186,7 @@ RemoteGDB::RiscvGdbRegCache::setRegs(ThreadContext *context) const context->setIntReg(i, r.gpr[i]); context->pcState(r.pc); for (int i = 0; i < NumFloatRegs; i++) - context->setFloatRegBits(i, r.fpr[i]); + context->setFloatReg(i, r.fpr[i]); context->setMiscReg(0, r.csr_base); context->setMiscReg(CSR_FFLAGS, r.fflags); diff --git a/src/arch/riscv/remote_gdb.hh b/src/arch/riscv/remote_gdb.hh index 739cb5a3e..adb438d24 100644 --- a/src/arch/riscv/remote_gdb.hh +++ b/src/arch/riscv/remote_gdb.hh @@ -61,7 +61,7 @@ class RemoteGDB : public BaseRemoteGDB struct { IntReg gpr[NumIntArchRegs]; IntReg pc; - FloatRegBits fpr[NumFloatRegs]; + FloatReg fpr[NumFloatRegs]; MiscReg csr_base; uint32_t fflags; |