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| author | Gabe Black <gabeblack@google.com> | 2019-10-29 19:31:37 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-11-18 20:02:31 +0000 |
| commit | 697e55995626f24658ce443287cd1ba90c2f68eb (patch) | |
| tree | 4f19d13ded04c4d4b3ae53607fa90638ba96a7bd /src/arch/riscv | |
| parent | 17a0c0b00644c37e9d8539a9de0a02dc213a6834 (diff) | |
| download | gem5-697e55995626f24658ce443287cd1ba90c2f68eb.tar.xz | |
arch: Make and use endian specific versions of the mem helpers.
Rather than using TheISA to pick an endian conversion function, we can
have a version defined for big and little endian and call the right one
from the ISA code.
Change-Id: I5014504968952e21abff3c5f6cbe58ca24233f33
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22373
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/riscv')
| -rw-r--r-- | src/arch/riscv/isa/formats/amo.isa | 12 | ||||
| -rw-r--r-- | src/arch/riscv/isa/formats/mem.isa | 8 |
2 files changed, 10 insertions, 10 deletions
diff --git a/src/arch/riscv/isa/formats/amo.isa b/src/arch/riscv/isa/formats/amo.isa index cc7346aa8..a115ccd93 100644 --- a/src/arch/riscv/isa/formats/amo.isa +++ b/src/arch/riscv/isa/formats/amo.isa @@ -227,7 +227,7 @@ def template LoadReservedExecute {{ %(ea_code)s; if (fault == NoFault) { - fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags); + fault = readMemAtomicLE(xc, traceData, EA, Mem, memAccessFlags); %(memacc_code)s; } @@ -256,7 +256,7 @@ def template StoreCondExecute {{ } if (fault == NoFault) { - fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, + fault = writeMemAtomicLE(xc, traceData, Mem, EA, memAccessFlags, &result); // RISC-V has the opposite convention gem5 has for success flags, // so we invert the result here. @@ -290,7 +290,7 @@ def template AtomicMemOpRMWExecute {{ assert(amo_op); if (fault == NoFault) { - fault = amoMemAtomic(xc, traceData, Mem, EA, memAccessFlags, + fault = amoMemAtomicLE(xc, traceData, Mem, EA, memAccessFlags, amo_op); %(memacc_code)s; } @@ -346,7 +346,7 @@ def template StoreCondInitiateAcc {{ } if (fault == NoFault) { - fault = writeMemTiming(xc, traceData, Mem, EA, + fault = writeMemTimingLE(xc, traceData, Mem, EA, memAccessFlags, nullptr); } @@ -394,7 +394,7 @@ def template LoadReservedCompleteAcc {{ %(op_decl)s; %(op_rd)s; - getMem(pkt, Mem, traceData); + getMemLE(pkt, Mem, traceData); if (fault == NoFault) { %(memacc_code)s; @@ -441,7 +441,7 @@ def template AtomicMemOpRMWCompleteAcc {{ %(op_decl)s; %(op_rd)s; - getMem(pkt, Mem, traceData); + getMemLE(pkt, Mem, traceData); if (fault == NoFault) { %(memacc_code)s; diff --git a/src/arch/riscv/isa/formats/mem.isa b/src/arch/riscv/isa/formats/mem.isa index a932d01cc..1e416d87e 100644 --- a/src/arch/riscv/isa/formats/mem.isa +++ b/src/arch/riscv/isa/formats/mem.isa @@ -106,7 +106,7 @@ def template LoadExecute {{ %(ea_code)s; if (fault == NoFault) { - fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags); + fault = readMemAtomicLE(xc, traceData, EA, Mem, memAccessFlags); %(memacc_code)s; } @@ -148,7 +148,7 @@ def template LoadCompleteAcc {{ %(op_decl)s; %(op_rd)s; - getMem(pkt, Mem, traceData); + getMemLE(pkt, Mem, traceData); if (fault == NoFault) { %(memacc_code)s; @@ -179,7 +179,7 @@ def template StoreExecute {{ } if (fault == NoFault) { - fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, + fault = writeMemAtomicLE(xc, traceData, Mem, EA, memAccessFlags, nullptr); } @@ -212,7 +212,7 @@ def template StoreInitiateAcc {{ } if (fault == NoFault) { - fault = writeMemTiming(xc, traceData, Mem, EA, + fault = writeMemTimingLE(xc, traceData, Mem, EA, memAccessFlags, nullptr); } |