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| author | Gabe Black <gabeblack@google.com> | 2020-01-29 15:41:59 -0800 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2020-02-01 12:31:40 +0000 |
| commit | 6a7a5b30050d10a7d9cc9cd5614988871253298d (patch) | |
| tree | 49f7d86b99e81b02e472e3c356366bce101415de /src/arch/riscv | |
| parent | dc328d00ebe798f0b0ee8903aca4256bb128dc6f (diff) | |
| download | gem5-6a7a5b30050d10a7d9cc9cd5614988871253298d.tar.xz | |
arch,sim: Merge initCPU and startupCPU.
These two functions were called in exactly one place one right after
the other, and served similar purposes.
This change merges them together, and cleans them up slightly. It also
removes checks for FullSystem, since those functions are only called
in full system to begin with.
Change-Id: I214f7d2d3f88960dccb5895c1241f61cd78716a8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24904
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/riscv')
| -rw-r--r-- | src/arch/riscv/utility.cc | 6 | ||||
| -rw-r--r-- | src/arch/riscv/utility.hh | 5 |
2 files changed, 3 insertions, 8 deletions
diff --git a/src/arch/riscv/utility.cc b/src/arch/riscv/utility.cc index 6e21a0484..949d7c66f 100644 --- a/src/arch/riscv/utility.cc +++ b/src/arch/riscv/utility.cc @@ -37,8 +37,8 @@ namespace RiscvISA void initCPU(ThreadContext *tc, int cpuId) { - static Fault reset = std::make_shared<Reset>(); - reset->invoke(tc); + Reset().invoke(tc); + tc->activate(); } -}
\ No newline at end of file +} diff --git a/src/arch/riscv/utility.hh b/src/arch/riscv/utility.hh index 6c0fcc130..f6e1f348a 100644 --- a/src/arch/riscv/utility.hh +++ b/src/arch/riscv/utility.hh @@ -117,11 +117,6 @@ getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp) return 0; } -inline void startupCPU(ThreadContext *tc, int cpuId) -{ - tc->activate(); -} - inline void copyRegs(ThreadContext *src, ThreadContext *dest) { |