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| author | Gabe Black <gabeblack@google.com> | 2019-10-29 15:12:10 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-11-02 00:01:52 +0000 |
| commit | 8549ee4a6dfc86a941cee0a478c01f6f2c146c3c (patch) | |
| tree | c6edb6d87332b970a6ffdcd518c4926cb86ce1e5 /src/arch/riscv | |
| parent | 5fa59a283148aec728320e2d527c0157edfa5b66 (diff) | |
| download | gem5-8549ee4a6dfc86a941cee0a478c01f6f2c146c3c.tar.xz | |
arch,cpu: Move endianness conversion of inst bytes into the ISA.
It doesn't matter if the bytes are converted before or after they're
fed into the decoder. The ISA already knows what endianness to use
implicitly, and this frees the CPU which doesn't from having to worry
about it.
Change-Id: Id6574ee81bbf4f032c1d7b2901a664f2bd014fbc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22343
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/riscv')
| -rw-r--r-- | src/arch/riscv/decoder.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/riscv/decoder.cc b/src/arch/riscv/decoder.cc index 41a52020e..69c392194 100644 --- a/src/arch/riscv/decoder.cc +++ b/src/arch/riscv/decoder.cc @@ -52,6 +52,7 @@ void Decoder::reset() void Decoder::moreBytes(const PCState &pc, Addr fetchPC, MachInst inst) { + inst = letoh(inst); DPRINTF(Decode, "Requesting bytes 0x%08x from address %#x\n", inst, fetchPC); |