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authorAlec Roelke <ar4jc@virginia.edu>2017-03-30 16:35:08 -0400
committerAlec Roelke <ar4jc@virginia.edu>2017-04-11 16:03:13 +0000
commitb17eeb2ae7a62e1f93ca295960a14c2e537bb3f1 (patch)
treeff33a50997e8f1a37c6356f47097c7494544bbcf /src/arch/riscv
parent3aada8ed5959f105fa51fbd815989e01f709b645 (diff)
downloadgem5-b17eeb2ae7a62e1f93ca295960a14c2e537bb3f1.tar.xz
riscv: Fix crashes with large or frequent mmaps
This patch fixes a bug where increasing the mmap region too much causes it to run into already-allocated memory, which causes gem5 to fail an assertion. Previously, the stack was incorrectly set up such that the end of the mmap region and the top of the stack were the same address and both would grow downward. With this patch, the top of the stack has been separated from the end of mmap and moved up, and the mmap region now grows upward instead of downward. [Rebase to master branch and remove dependencies.] Change-Id: I7271ff478fff2994f918bc5003a6139b9ba6a520 Reviewed-on: https://gem5-review.googlesource.com/2680 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/arch/riscv')
-rw-r--r--src/arch/riscv/process.cc5
-rw-r--r--src/arch/riscv/process.hh4
2 files changed, 6 insertions, 3 deletions
diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index b9623720e..13038c17c 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -60,13 +60,12 @@ using namespace RiscvISA;
RiscvProcess::RiscvProcess(ProcessParams * params,
ObjectFile *objFile) : Process(params, objFile)
{
- const Addr mem_base = 0x80000000;
- const Addr stack_base = mem_base;
+ const Addr stack_base = 0x7FFFFFFFFFFFFFFFL;
const Addr max_stack_size = PageBytes * 64;
const Addr next_thread_stack_base = stack_base - max_stack_size;
const Addr brk_point = roundUp(objFile->bssBase() + objFile->bssSize(),
PageBytes);
- const Addr mmap_end = mem_base;
+ const Addr mmap_end = 0x4000000000000000L;
memState = make_shared<MemState>(brk_point, stack_base, max_stack_size,
next_thread_stack_base, mmap_end);
}
diff --git a/src/arch/riscv/process.hh b/src/arch/riscv/process.hh
index 8275a118a..f732a4436 100644
--- a/src/arch/riscv/process.hh
+++ b/src/arch/riscv/process.hh
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2006 The Regents of The University of Michigan
+ * Copyright (c) 2017 The University of Virginia
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -27,6 +28,7 @@
*
* Authors: Gabe Black
* Ali Saidi
+ * Alec Roelke
*/
#ifndef __RISCV_PROCESS_HH__
@@ -57,6 +59,8 @@ class RiscvProcess : public Process
using Process::getSyscallArg;
void setSyscallArg(ThreadContext *tc, int i, RiscvISA::IntReg val);
void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);
+
+ virtual bool mmapGrowsDown() const override { return false; }
};
/* No architectural page table defined for this ISA */