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authorGabe Black <gabeblack@google.com>2019-10-29 18:56:27 -0700
committerGabe Black <gabeblack@google.com>2019-11-18 20:02:31 +0000
commitd40f0bc579fb8b10da7181d3a144cd3e9a0a0e59 (patch)
treeeb0a80fd0a21017befa4eee8c4e77380bb1b4657 /src/arch/riscv
parent697e55995626f24658ce443287cd1ba90c2f68eb (diff)
downloadgem5-d40f0bc579fb8b10da7181d3a144cd3e9a0a0e59.tar.xz
arch: Get rid of the (Big|Little)EndianGuest namespaces.
These namespaces were used to set up an environment/context where there was an implicit guest namespace. This is an issue when there may be multiple guest endiannesses which might be different. In cases where we don't know what the guest endianness is, we can't rely on it being an implicit part of our context since that would be ambiguous. In cases where we do know, for instance in ISA specific code, we can just use the endianness specific version that's appropriate for that context. This also (somewhat) removes the assumption that there is a single endianness that applies for a particular ISA. Practically speaking this assumption will probably still stand though, since there would likely be a non-trivial performance penalty to apply a configurable endianness instead of a fixed one the compiler can optomize/remove. Change-Id: I2dff338b58726d724f387388efe32d9233885680 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22374 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/riscv')
-rw-r--r--src/arch/riscv/isa_traits.hh4
-rw-r--r--src/arch/riscv/system.cc2
2 files changed, 1 insertions, 5 deletions
diff --git a/src/arch/riscv/isa_traits.hh b/src/arch/riscv/isa_traits.hh
index abafad2e2..f69e71994 100644
--- a/src/arch/riscv/isa_traits.hh
+++ b/src/arch/riscv/isa_traits.hh
@@ -50,12 +50,10 @@
#include "base/types.hh"
#include "cpu/static_inst_fwd.hh"
-namespace LittleEndianGuest {}
-
namespace RiscvISA
{
-using namespace LittleEndianGuest;
+const ByteOrder GuestByteOrder = LittleEndianByteOrder;
const Addr PageShift = 12;
const Addr PageBytes = ULL(1) << PageShift;
diff --git a/src/arch/riscv/system.cc b/src/arch/riscv/system.cc
index 88d6251cc..2017eed98 100644
--- a/src/arch/riscv/system.cc
+++ b/src/arch/riscv/system.cc
@@ -42,8 +42,6 @@
#include "params/RiscvSystem.hh"
#include "sim/byteswap.hh"
-using namespace LittleEndianGuest;
-
RiscvSystem::RiscvSystem(Params *p)
: System(p),
_isBareMetal(p->bare_metal),