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| author | Andreas Sandberg <Andreas.Sandberg@arm.com> | 2013-01-07 13:05:35 -0500 |
|---|---|---|
| committer | Andreas Sandberg <Andreas.Sandberg@arm.com> | 2013-01-07 13:05:35 -0500 |
| commit | 3db3f83a5ea4b9565db1ab6b22d18e2b33ecef98 (patch) | |
| tree | a736f3746d5c38bdc98d6fb8589113556271d486 /src/arch/sparc/SConscript | |
| parent | 69d419f31383ac7801e1debb62d5bbf7cb899e3c (diff) | |
| download | gem5-3db3f83a5ea4b9565db1ab6b22d18e2b33ecef98.tar.xz | |
arch: Make the ISA class inherit from SimObject
The ISA class on stores the contents of ID registers on many
architectures. In order to make reset values of such registers
configurable, we make the class inherit from SimObject, which allows
us to use the normal generated parameter headers.
This patch introduces a Python helper method, BaseCPU.createThreads(),
which creates a set of ISAs for each of the threads in an SMT
system. Although it is currently only needed when creating
multi-threaded CPUs, it should always be called before instantiating
the system as this is an obvious place to configure ID registers
identifying a thread/CPU.
Diffstat (limited to 'src/arch/sparc/SConscript')
| -rw-r--r-- | src/arch/sparc/SConscript | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript index 5e2146750..28949aaaf 100644 --- a/src/arch/sparc/SConscript +++ b/src/arch/sparc/SConscript @@ -53,6 +53,7 @@ if env['TARGET_ISA'] == 'sparc': Source('vtophys.cc') SimObject('SparcInterrupts.py') + SimObject('SparcISA.py') SimObject('SparcNativeTrace.py') SimObject('SparcSystem.py') SimObject('SparcTLB.py') |