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authorNathan Binkert <nate@binkert.org>2007-07-26 23:15:49 -0700
committerNathan Binkert <nate@binkert.org>2007-07-26 23:15:49 -0700
commitf0fef8f850b0c5aa73337ca11b26169163b2b2e1 (patch)
treed49d3492618ee85717554cddbe62cba1b5e7fb9c /src/arch/sparc/SparcTLB.py
parent6b73ff43ff58502c80050c7aeff5a08a4ce61f87 (diff)
parentcda354b07035f73a3b220f89014721300d36a815 (diff)
downloadgem5-f0fef8f850b0c5aa73337ca11b26169163b2b2e1.tar.xz
Merge python and x86 changes with cache branch
--HG-- extra : convert_revision : e06a950964286604274fba81dcca362d75847233
Diffstat (limited to 'src/arch/sparc/SparcTLB.py')
-rw-r--r--src/arch/sparc/SparcTLB.py6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/arch/sparc/SparcTLB.py b/src/arch/sparc/SparcTLB.py
index 30e5ebb08..2d0257cd7 100644
--- a/src/arch/sparc/SparcTLB.py
+++ b/src/arch/sparc/SparcTLB.py
@@ -35,8 +35,14 @@ class SparcTLB(SimObject):
class SparcDTB(SparcTLB):
type = 'SparcDTB'
+ cxx_namespace = 'SparcISA'
+ cxx_class = 'DTB'
+
size = 64
class SparcITB(SparcTLB):
type = 'SparcITB'
+ cxx_namespace = 'SparcISA'
+ cxx_class = 'ITB'
+
size = 64