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author | Ali Saidi <saidi@eecs.umich.edu> | 2006-12-09 18:00:40 -0500 |
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committer | Ali Saidi <saidi@eecs.umich.edu> | 2006-12-09 18:00:40 -0500 |
commit | 81a00fdcfef4ecffd57a909db67ca0ff3b99de3a (patch) | |
tree | a80cc38ae0827b41f66560750606bb9061955481 /src/arch/sparc/faults.cc | |
parent | ed22eb781dc7714c1b2ca17cf17824917e38319c (diff) | |
download | gem5-81a00fdcfef4ecffd57a909db67ca0ff3b99de3a.tar.xz |
Allocate the correct number of global registers
Fix fault formating and code for traps
fix a couple of bugs in the decoder
Cleanup/fix page table entry code
Implement more mmaped iprs, fix numbered tlb insertion code, add function to dump tlb contents
Don't panic if we differ from legion on a tcc instruction because of where legion prints its data and where we print our data
src/arch/sparc/faults.cc:
Fix fault formating and code for traps
src/arch/sparc/intregfile.hh:
allocate the correct number of global registers
src/arch/sparc/isa/decoder.isa:
fix a couple of bugs in the decoder: wrasi should write asi not ccr, done/retry should get hpstate from htstate
src/arch/sparc/pagetable.hh:
cleanup/fix page table code
src/arch/sparc/tlb.cc:
implement more mmaped iprs, fix numbered insertion code, add function to dump tlb contents
src/arch/sparc/tlb.hh:
add functions to write TagAccess register on tlb miss and to dump all tlb entries for debugging
src/cpu/exetrace.cc:
dump tlb entries on error, don't consider differences the cycle we take a trap to be bad.
--HG--
extra : convert_revision : d7d771900f6f25219f3dc6a6e51986d342a32e03
Diffstat (limited to 'src/arch/sparc/faults.cc')
-rw-r--r-- | src/arch/sparc/faults.cc | 20 |
1 files changed, 6 insertions, 14 deletions
diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc index 78b2b4b76..64cfc832a 100644 --- a/src/arch/sparc/faults.cc +++ b/src/arch/sparc/faults.cc @@ -551,34 +551,26 @@ void SparcFaultBase::invoke(ThreadContext * tc) PrivilegeLevel level = getNextLevel(current); - if(HPSTATE & (1 << 5) || TL == MaxTL - 1) - { + if(HPSTATE & (1 << 5) || TL == MaxTL - 1) { getREDVector(5, PC, NPC); doREDFault(tc, TT); //This changes the hpstate and pstate, so we need to make sure we //save the old version on the trap stack in doREDFault. enterREDState(tc); - } - else if(TL == MaxTL) - { + } else if(TL == MaxTL) { panic("Should go to error state here.. crap\n"); //Do error_state somehow? //Probably inject a WDR fault using the interrupt mechanism. //What should the PC and NPC be set to? - } - else if(TL > MaxPTL && level == Privileged) - { + } else if(TL > MaxPTL && level == Privileged) { //guest_watchdog fault doNormalFault(tc, trapType(), true); getHyperVector(tc, PC, NPC, 2); - } - else if(level == Hyperprivileged) - { + } else if(level == Hyperprivileged || + level == Privileged && trapType() >= 384) { doNormalFault(tc, trapType(), true); getHyperVector(tc, PC, NPC, trapType()); - } - else - { + } else { doNormalFault(tc, trapType(), false); getPrivVector(tc, PC, NPC, trapType(), TL+1); } |