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| author | Kevin Lim <ktlim@umich.edu> | 2006-11-02 15:20:37 -0500 |
|---|---|---|
| committer | Kevin Lim <ktlim@umich.edu> | 2006-11-02 15:20:37 -0500 |
| commit | 45363ea658251df0c31a75d7bd5d0ac3a3809623 (patch) | |
| tree | bae91271cf1e57d6cacbf0bbe4853f0db0067797 /src/arch/sparc/faults.cc | |
| parent | c3485a654888f641dca23128f8197ef747c706d2 (diff) | |
| download | gem5-45363ea658251df0c31a75d7bd5d0ac3a3809623.tar.xz | |
Have bus use the BadAddress device to handle bad addresses. The O3 CPU should be able to boot into Linux with caches on after this change.
src/mem/bus.cc:
src/mem/bus.hh:
Bus now will be setup with a default responder, unless the user overrides it. This default responder should return BadAddress if no matching port is found.
src/python/m5/objects/Bus.py:
Bus now has a default responder for FS mode if the user doesn't override it. It returns BadAddress if no matching port is found.
src/python/m5/objects/Tsunami.py:
Add bad address device. Also record when the user has specified their own default responder.
--HG--
extra : convert_revision : 59070477ae313ee711b2d59baa2369c9a91c5b85
Diffstat (limited to 'src/arch/sparc/faults.cc')
0 files changed, 0 insertions, 0 deletions