arch: ISA parser additions of vector registers

Reiley's update :) of the isa parser definitions. My addition of the
vector element operand concept for the ISA parser. Nathanael's modification
creating a hierarchy between vector registers and its constituencies to the
isa parser.

Some fixes/updates on top to consider instructions as vectors instead of
floating when they use the VectorRF. Some counters added to all the
models to keep faithful counts.

Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2706
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

1 files changed, 6 insertions, 0 deletions

diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index c09bd0da2..13e9c19f6 100644
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -108,6 +108,12 @@ template<> SparcFaultBase::FaultVals
     SparcFault<FpDisabled>::vals =
 {"fp_disabled", 0x020, 800, {P, P, H}, FaultStat()};
 
+/* SPARCv8 and SPARCv9 define just fp_disabled trap. SIMD is not contemplated
+ * as a separate part. Therefore, we use the same code and TT */
+template<> SparcFaultBase::FaultVals
+    SparcFault<VecDisabled>::vals =
+{"fp_disabled", 0x020, 800, {P, P, H}, FaultStat()};
+
 template<> SparcFaultBase::FaultVals
     SparcFault<FpExceptionIEEE754>::vals =
 {"fp_exception_ieee_754", 0x021, 1110, {P, P, H}, FaultStat()};