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authorGabe Black <gblack@eecs.umich.edu>2007-03-07 20:04:46 +0000
committerGabe Black <gblack@eecs.umich.edu>2007-03-07 20:04:46 +0000
commit54fc750924ebeeb34d598018b664a886cc3f7ac5 (patch)
tree87f21e528a20ac3d44540922a1ebc0e7df3e9389 /src/arch/sparc/faults.cc
parent8edc9d79cee3edd6d16a8254a0180aaa242974c7 (diff)
downloadgem5-54fc750924ebeeb34d598018b664a886cc3f7ac5.tar.xz
Move the magic m5 PageTableFault into sim/faults.[hh,cc] since it's the same across all architectures.
--HG-- extra : convert_revision : 18d441eb7ac44df4df41771bfe3dec69f7fa70ec
Diffstat (limited to 'src/arch/sparc/faults.cc')
-rw-r--r--src/arch/sparc/faults.cc28
1 files changed, 0 insertions, 28 deletions
diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index f6cf97872..88c086090 100644
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -267,12 +267,6 @@ template<> SparcFaultBase::FaultVals
SparcFault<TrapInstruction>::vals =
{"trap_instruction", 0x100, 1602, {P, P, H}};
-#if !FULL_SYSTEM
-template<> SparcFaultBase::FaultVals
- SparcFault<PageTableFault>::vals =
- {"page_table_fault", 0x0000, 0, {SH, SH, SH}};
-#endif
-
/**
* This causes the thread context to enter RED state. This causes the side
* effects which go with entering RED state because of a trap.
@@ -680,28 +674,6 @@ void TrapInstruction::invoke(ThreadContext *tc)
tc->setNextNPC(tc->readNextNPC() + sizeof(MachInst));
}
-void PageTableFault::invoke(ThreadContext *tc)
-{
- Process *p = tc->getProcessPtr();
-
- // We've accessed the next page of the stack, so extend the stack
- // to cover it.
- if(vaddr < p->stack_min && vaddr >= p->stack_min - PageBytes)
- {
- p->stack_min -= PageBytes;
- if(p->stack_base - p->stack_min > 8*1024*1024)
- fatal("Over max stack size for one thread\n");
- p->pTable->allocate(p->stack_min, PageBytes);
- warn("Increasing stack size by one page.");
- }
- // Otherwise, we have an unexpected page fault. Report that fact,
- // and what address was accessed to cause the fault.
- else
- {
- panic("Page table fault when accessing virtual address %#x\n", vaddr);
- }
-}
-
#endif
} // namespace SparcISA