diff options
| author | Gabe Black <gabeblack@google.com> | 2018-10-18 17:50:42 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-01-22 21:16:10 +0000 |
| commit | 1ab1500dfd0cb64b2fef7fb5e0f9e1fa007d2481 (patch) | |
| tree | e2c9cbab3738a79463e6ad9defbe845efb764a51 /src/arch/sparc/faults.hh | |
| parent | 230b892fa3f484a46f4cd77f889f8793416b91e2 (diff) | |
| download | gem5-1ab1500dfd0cb64b2fef7fb5e0f9e1fa007d2481.tar.xz | |
sparc: Get rid of some register type definitions.
These are IntReg, FloatReg, FloatRegBits, and MiscReg. These have been
supplanted by the global types RegVal and FloatRegVal.
Change-Id: I956abfc7b439b083403e1a0d01e0bb35020bde44
Reviewed-on: https://gem5-review.googlesource.com/c/13627
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/arch/sparc/faults.hh')
| -rw-r--r-- | src/arch/sparc/faults.hh | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/sparc/faults.hh b/src/arch/sparc/faults.hh index 88826bf61..2c44d51d4 100644 --- a/src/arch/sparc/faults.hh +++ b/src/arch/sparc/faults.hh @@ -354,12 +354,12 @@ void doREDFault(ThreadContext *tc, TrapType tt); void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv); -void getREDVector(MiscReg TT, Addr &PC, Addr &NPC); +void getREDVector(RegVal TT, Addr &PC, Addr &NPC); -void getHyperVector(ThreadContext * tc, Addr &PC, Addr &NPC, MiscReg TT); +void getHyperVector(ThreadContext * tc, Addr &PC, Addr &NPC, RegVal TT); -void getPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, MiscReg TT, - MiscReg TL); +void getPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, RegVal TT, + RegVal TL); } // namespace SparcISA |