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author | Gabe Black <gabeblack@google.com> | 2017-11-06 23:01:03 -0800 |
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committer | Gabe Black <gabeblack@google.com> | 2017-11-22 00:23:52 +0000 |
commit | 315f7d25f3f423577140d7b9f1051a20f5ac51ef (patch) | |
tree | 5a006e13c868fd9e5d66a5545479b3c645d88e62 /src/arch/sparc/insts/micro.hh | |
parent | bd96f10f997de75d31192cb232f50c37b4a11eac (diff) | |
download | gem5-315f7d25f3f423577140d7b9f1051a20f5ac51ef.tar.xz |
sparc: Move the microop/macroop base classes out of the ISA desc.
These were just raw C++ classes.
Change-Id: Id2101400d885c6938efb6b94f2949722cfbb94ae
Reviewed-on: https://gem5-review.googlesource.com/5481
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/arch/sparc/insts/micro.hh')
-rw-r--r-- | src/arch/sparc/insts/micro.hh | 126 |
1 files changed, 126 insertions, 0 deletions
diff --git a/src/arch/sparc/insts/micro.hh b/src/arch/sparc/insts/micro.hh new file mode 100644 index 000000000..d8c3adc33 --- /dev/null +++ b/src/arch/sparc/insts/micro.hh @@ -0,0 +1,126 @@ +/* + * Copyright (c) 2006-2007 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __ARCH_SPARC_INSTS_MICRO_HH__ +#define __ARCH_SPARC_INSTS_MICRO_HH__ + +#include "arch/sparc/insts/static_inst.hh" + +namespace SparcISA +{ + +class SparcMacroInst : public SparcStaticInst +{ + protected: + const uint32_t numMicroops; + + // Constructor. + SparcMacroInst(const char *mnem, ExtMachInst _machInst, + OpClass __opClass, uint32_t _numMicroops) : + SparcStaticInst(mnem, _machInst, __opClass), + numMicroops(_numMicroops) + { + assert(numMicroops); + microops = new StaticInstPtr[numMicroops]; + flags[IsMacroop] = true; + } + + ~SparcMacroInst() + { + delete [] microops; + } + + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; + + StaticInstPtr *microops; + + StaticInstPtr + fetchMicroop(MicroPC upc) const override + { + assert(upc < numMicroops); + return microops[upc]; + } + + Fault + execute(ExecContext *, Trace::InstRecord *) const override + { + panic("Tried to execute a macroop directly!\n"); + } + + Fault + initiateAcc(ExecContext *, Trace::InstRecord *) const override + { + panic("Tried to execute a macroop directly!\n"); + } + + Fault + completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const override + { + panic("Tried to execute a macroop directly!\n"); + } +}; + +class SparcMicroInst : public SparcStaticInst +{ + protected: + // Constructor. + SparcMicroInst(const char *mnem, ExtMachInst _machInst, + OpClass __opClass) : + SparcStaticInst(mnem, _machInst, __opClass) + { + flags[IsMicroop] = true; + } + + void + advancePC(SparcISA::PCState &pcState) const override + { + if (flags[IsLastMicroop]) + pcState.uEnd(); + else + pcState.uAdvance(); + } +}; + +class SparcDelayedMicroInst : public SparcMicroInst +{ + protected: + // Constructor. + SparcDelayedMicroInst(const char *mnem, ExtMachInst _machInst, + OpClass __opClass) : + SparcMicroInst(mnem, _machInst, __opClass) + { + flags[IsDelayedCommit] = true; + } +}; + +} + +#endif // __ARCH_SPARC_INSTS_MICRO_HH__ |