sparc: Pull more StaticInst base classes out of the ISA desc.

These are for the trap and branch instructions.

Change-Id: Idedab6f3e6c6c954c1f8a36dae52976cf25ad394
Reviewed-on: https://gem5-review.googlesource.com/5461
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

5 files changed, 355 insertions, 0 deletions

diff --git a/src/arch/sparc/insts/SConscript b/src/arch/sparc/insts/SConscript
index 1e2797351..24b74858e 100644
--- a/src/arch/sparc/insts/SConscript
+++ b/src/arch/sparc/insts/SConscript
@@ -32,5 +32,7 @@
 Import('*')
 
 if env['TARGET_ISA'] == 'sparc':
+    Source('branch.cc')
     Source('priv.cc')
     Source('static_inst.cc')
+    Source('trap.cc')
diff --git a/src/arch/sparc/insts/branch.cc b/src/arch/sparc/insts/branch.cc
new file mode 100644
index 000000000..a49fd8c5c
--- /dev/null
+++ b/src/arch/sparc/insts/branch.cc
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2006-2007 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ *          Steve Reinhardt
+ */
+
+#include "arch/sparc/insts/branch.hh"
+
+////////////////////////////////////////////////////////////////////
+//
+// Branch instructions
+//
+
+namespace SparcISA
+{
+
+template class BranchNBits<19>;
+template class BranchNBits<22>;
+template class BranchNBits<30>;
+
+std::string
+Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    std::stringstream response;
+
+    printMnemonic(response, mnemonic);
+    printRegArray(response, _srcRegIdx, _numSrcRegs);
+    if (_numDestRegs && _numSrcRegs)
+            response << ", ";
+    printDestReg(response, 0);
+
+    return response.str();
+}
+
+std::string
+BranchImm13::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    std::stringstream response;
+
+    printMnemonic(response, mnemonic);
+    printRegArray(response, _srcRegIdx, _numSrcRegs);
+    if (_numSrcRegs > 0)
+        response << ", ";
+    ccprintf(response, "0x%x", imm);
+    if (_numDestRegs > 0)
+        response << ", ";
+    printDestReg(response, 0);
+
+    return response.str();
+}
+
+std::string
+BranchDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    std::stringstream response;
+    std::string symbol;
+    Addr symbol_addr;
+
+    Addr target = disp + pc;
+
+    printMnemonic(response, mnemonic);
+    ccprintf(response, "0x%x", target);
+
+    if (symtab && symtab->findNearestSymbol(target, symbol, symbol_addr)) {
+        ccprintf(response, " <%s", symbol);
+        if (symbol_addr != target)
+            ccprintf(response, "+%d>", target - symbol_addr);
+        else
+            ccprintf(response, ">");
+    }
+
+    return response.str();
+}
+
+}
diff --git a/src/arch/sparc/insts/branch.hh b/src/arch/sparc/insts/branch.hh
new file mode 100644
index 000000000..544b049d3
--- /dev/null
+++ b/src/arch/sparc/insts/branch.hh
@@ -0,0 +1,123 @@
+/*
+ * Copyright (c) 2006-2007 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ *          Steve Reinhardt
+ */
+
+#ifndef __ARCH_SPARC_INSTS_BRANCH_HH__
+#define __ARCH_SPARC_INSTS_BRANCH_HH__
+
+#include "arch/sparc/insts/static_inst.hh"
+
+////////////////////////////////////////////////////////////////////
+//
+// Branch instructions
+//
+
+namespace SparcISA
+{
+
+/**
+ * Base class for branch operations.
+ */
+class Branch : public SparcStaticInst
+{
+  protected:
+    using SparcStaticInst::SparcStaticInst;
+
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
+};
+
+/**
+ * Base class for branch operations with an immediate displacement.
+ */
+class BranchDisp : public Branch
+{
+  protected:
+    BranchDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
+               int32_t _disp) :
+        Branch(mnem, _machInst, __opClass), disp(_disp)
+    {}
+
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
+
+    int32_t disp;
+};
+
+/**
+ * Base class for branches with n bit displacements.
+ */
+template<int bits>
+class BranchNBits : public BranchDisp
+{
+  protected:
+    // Constructor
+    BranchNBits(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
+        BranchDisp(mnem, _machInst, __opClass,
+                   sext<bits + 2>((_machInst & mask(bits)) << 2))
+    {}
+};
+
+/**
+ * Base class for 16bit split displacements.
+ */
+class BranchSplit : public BranchDisp
+{
+  protected:
+    // Constructor
+    BranchSplit(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
+        BranchDisp(mnem, _machInst, __opClass,
+                   sext<18>((bits(_machInst, 21, 20) << 16) |
+                            (bits(_machInst, 13, 0) << 2)))
+    {}
+};
+
+/**
+ * Base class for branches that use an immediate and a register to
+ * compute their displacements.
+ */
+class BranchImm13 : public Branch
+{
+  protected:
+    // Constructor
+    BranchImm13(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
+        Branch(mnem, _machInst, __opClass),
+        imm(sext<13>(bits(_machInst, 12, 0)))
+    {}
+
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
+
+    int32_t imm;
+};
+
+}
+
+#endif // __ARCH_SPARC_INSTS_BRANCH_HH__
diff --git a/src/arch/sparc/insts/trap.cc b/src/arch/sparc/insts/trap.cc
new file mode 100644
index 000000000..e75d153b9
--- /dev/null
+++ b/src/arch/sparc/insts/trap.cc
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2006-2007 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ *          Steve Reinhardt
+ */
+
+#include "arch/sparc/insts/trap.hh"
+
+namespace SparcISA
+{
+
+std::string
+Trap::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    std::stringstream response;
+
+    printMnemonic(response, mnemonic);
+    ccprintf(response, " ");
+    printReg(response, _srcRegIdx[0]);
+    ccprintf(response, ", 0x%x", trapNum);
+    ccprintf(response, ", or ");
+    printReg(response, _srcRegIdx[1]);
+    return response.str();
+}
+
+}
diff --git a/src/arch/sparc/insts/trap.hh b/src/arch/sparc/insts/trap.hh
new file mode 100644
index 000000000..939647a96
--- /dev/null
+++ b/src/arch/sparc/insts/trap.hh
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2006-2007 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ *          Steve Reinhardt
+ */
+
+////////////////////////////////////////////////////////////////////
+//
+// Trap instructions
+//
+
+#ifndef __ARCH_SPARC_INSTS_TRAP_HH__
+#define __ARCH_SPARC_INSTS_TRAP_HH__
+
+#include "arch/sparc/insts/static_inst.hh"
+
+namespace SparcISA
+{
+
+/**
+ * Base class for trap instructions,
+ * or instructions that always fault.
+ */
+class Trap : public SparcStaticInst
+{
+  protected:
+
+    // Constructor
+    Trap(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
+        SparcStaticInst(mnem, _machInst, __opClass),
+        trapNum(bits(_machInst, 7, 0))
+    {}
+
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
+
+    int trapNum;
+};
+
+class FpUnimpl : public SparcStaticInst
+{
+  protected:
+    using SparcStaticInst::SparcStaticInst;
+
+    std::string
+    generateDisassembly(Addr pc,  const SymbolTable *symtab) const override
+    {
+        return mnemonic;
+    }
+};
+
+}
+
+#endif // __ARCH_SPARC_INSTS_TRAP_HH__