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author | Ali Saidi <saidi@eecs.umich.edu> | 2007-02-02 18:05:21 -0500 |
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committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-02-02 18:05:21 -0500 |
commit | 665ddde57a2f6de6cafd5046f3ee00297e992ce0 (patch) | |
tree | 1c86514c6e07ee4641e54a298b137ff635d81bf9 /src/arch/sparc/interrupts.hh | |
parent | 592f35ac0ff8d525fad2dc606b53b4cd8b84fd69 (diff) | |
download | gem5-665ddde57a2f6de6cafd5046f3ee00297e992ce0.tar.xz |
make interrupt code serialize itself and fix indenting
--HG--
extra : convert_revision : d0bb23c7922568586b640084ac719e809cc8422f
Diffstat (limited to 'src/arch/sparc/interrupts.hh')
-rw-r--r-- | src/arch/sparc/interrupts.hh | 254 |
1 files changed, 129 insertions, 125 deletions
diff --git a/src/arch/sparc/interrupts.hh b/src/arch/sparc/interrupts.hh index 99ddb4919..42bbfc5cf 100644 --- a/src/arch/sparc/interrupts.hh +++ b/src/arch/sparc/interrupts.hh @@ -46,161 +46,165 @@ enum interrupts_t { num_interrupt_types }; - class Interrupts - { +class Interrupts +{ - private: + private: - bool interrupts[num_interrupt_types]; - int numPosted; + bool interrupts[num_interrupt_types]; + int numPosted; - public: - Interrupts() - { - for (int i = 0; i < num_interrupt_types; ++i) { - interrupts[i] = false; - } - numPosted = 0; - } - - void post(int int_type) - { - if (int_type < 0 || int_type >= num_interrupt_types) - panic("posting unknown interrupt!\n"); - interrupts[int_type] = true; - ++numPosted; + public: + Interrupts() + { + for (int i = 0; i < num_interrupt_types; ++i) { + interrupts[i] = false; } + numPosted = 0; + } - void post(int int_num, int index) - { + void post(int int_type) + { + if (int_type < 0 || int_type >= num_interrupt_types) + panic("posting unknown interrupt!\n"); + interrupts[int_type] = true; + ++numPosted; + } - } + void post(int int_num, int index) + { - void clear(int int_num, int index) - { + } - } + void clear(int int_num, int index) + { - void clear_all() - { + } - } + void clear_all() + { - bool check_interrupts(ThreadContext * tc) const - { - if (numPosted) - return true; - else - return false; - } + } - Fault getInterrupt(ThreadContext * tc) - { - int hpstate = tc->readMiscReg(MISCREG_HPSTATE); - int pstate = tc->readMiscReg(MISCREG_PSTATE); - bool ie = pstate & PSTATE::ie; - - // THESE ARE IN ORDER OF PRIORITY - // since there are early returns, and the highest - // priority interrupts should get serviced, - // it is v. important that new interrupts are inserted - // in the right order of processing - if (hpstate & HPSTATE::hpriv) { - if (ie) { - if (interrupts[hstick_match]) { - if (tc->readMiscReg(MISCREG_HINTP) & 1) { - interrupts[hstick_match] = false; - --numPosted; - return new HstickMatch; - } - } - if (interrupts[interrupt_vector]) { - interrupts[interrupt_vector] = false; - --numPosted; - //HAVEN'T IMPLed THIS YET - return NoFault; - } - } else { - if (interrupts[hstick_match]) { - return NoFault; - } + bool check_interrupts(ThreadContext * tc) const + { + if (numPosted) + return true; + else + return false; + } - } - } else { - if (interrupts[trap_level_zero]) { - if ((pstate & HPSTATE::tlz) && (tc->readMiscReg(MISCREG_TL) == 0)) { - interrupts[trap_level_zero] = false; - --numPosted; - return new TrapLevelZero; - } - } + Fault getInterrupt(ThreadContext * tc) + { + int hpstate = tc->readMiscReg(MISCREG_HPSTATE); + int pstate = tc->readMiscReg(MISCREG_PSTATE); + bool ie = pstate & PSTATE::ie; + + // THESE ARE IN ORDER OF PRIORITY + // since there are early returns, and the highest + // priority interrupts should get serviced, + // it is v. important that new interrupts are inserted + // in the right order of processing + if (hpstate & HPSTATE::hpriv) { + if (ie) { if (interrupts[hstick_match]) { if (tc->readMiscReg(MISCREG_HINTP) & 1) { interrupts[hstick_match] = false; --numPosted; return new HstickMatch; - } - } - if (ie) { - if (interrupts[cpu_mondo]) { - interrupts[cpu_mondo] = false; - --numPosted; - return new CpuMondo; } - if (interrupts[dev_mondo]) { - interrupts[dev_mondo] = false; - --numPosted; - return new DevMondo; + } + if (interrupts[interrupt_vector]) { + interrupts[interrupt_vector] = false; + --numPosted; + //HAVEN'T IMPLed THIS YET + return NoFault; + } + } else { + if (interrupts[hstick_match]) { + return NoFault; + } + + } + } else { + if (interrupts[trap_level_zero]) { + if ((pstate & HPSTATE::tlz) && (tc->readMiscReg(MISCREG_TL) == 0)) { + interrupts[trap_level_zero] = false; + --numPosted; + return new TrapLevelZero; + } + } + if (interrupts[hstick_match]) { + if (tc->readMiscReg(MISCREG_HINTP) & 1) { + interrupts[hstick_match] = false; + --numPosted; + return new HstickMatch; } - if (interrupts[soft_interrupt]) { - int il = InterruptLevel(tc->readMiscReg(MISCREG_SOFTINT)); - // it seems that interrupt vectors are right in - // the middle of interrupt levels with regard to - // priority, so have to check - if ((il < 6) && - interrupts[interrupt_vector]) { - // may require more details here since there - // may be lots of interrupts embedded in an - // platform interrupt vector - interrupts[interrupt_vector] = false; + } + if (ie) { + if (interrupts[cpu_mondo]) { + interrupts[cpu_mondo] = false; + --numPosted; + return new CpuMondo; + } + if (interrupts[dev_mondo]) { + interrupts[dev_mondo] = false; + --numPosted; + return new DevMondo; + } + if (interrupts[soft_interrupt]) { + int il = InterruptLevel(tc->readMiscReg(MISCREG_SOFTINT)); + // it seems that interrupt vectors are right in + // the middle of interrupt levels with regard to + // priority, so have to check + if ((il < 6) && + interrupts[interrupt_vector]) { + // may require more details here since there + // may be lots of interrupts embedded in an + // platform interrupt vector + interrupts[interrupt_vector] = false; + --numPosted; + //HAVEN'T IMPLed YET + return NoFault; + } else { + if (il > tc->readMiscReg(MISCREG_PIL)) { + uint64_t si = tc->readMiscReg(MISCREG_SOFTINT); + uint64_t more = si & ~(1 << (il + 1)); + if (!InterruptLevel(more)) { + interrupts[soft_interrupt] = false; --numPosted; - //HAVEN'T IMPLed YET - return NoFault; - } else { - if (il > tc->readMiscReg(MISCREG_PIL)) { - uint64_t si = tc->readMiscReg(MISCREG_SOFTINT); - uint64_t more = si & ~(1 << (il + 1)); - if (!InterruptLevel(more)) { - interrupts[soft_interrupt] = false; - --numPosted; - } - return new InterruptLevelN(il); } + return new InterruptLevelN(il); } } - if (interrupts[resumable_error]) { - interrupts[resumable_error] = false; - --numPosted; - return new ResumableError; - } + } + if (interrupts[resumable_error]) { + interrupts[resumable_error] = false; + --numPosted; + return new ResumableError; } } - return NoFault; } + return NoFault; + } - void updateIntrInfo(ThreadContext * tc) - { + void updateIntrInfo(ThreadContext * tc) + { - } + } - void serialize(std::ostream &os) - { - } + void serialize(std::ostream &os) + { + SERIALIZE_ARRAY(interrupts,num_interrupt_types); + SERIALIZE_SCALAR(numPosted); + } - void unserialize(Checkpoint *cp, const std::string §ion) - { - } - }; -} + void unserialize(Checkpoint *cp, const std::string §ion) + { + UNSERIALIZE_ARRAY(interrupts,num_interrupt_types); + UNSERIALIZE_SCALAR(numPosted); + } +}; +} // namespace SPARC_ISA #endif // __ARCH_SPARC_INTERRUPT_HH__ |