Allocate the correct number of global registers

Fix fault formating and code for traps
fix a couple of bugs in the decoder
Cleanup/fix page table entry code
Implement more mmaped iprs, fix numbered tlb insertion code, add function to dump tlb contents
Don't panic if we differ from legion on a tcc instruction because of where legion prints its data and where we print our data

src/arch/sparc/faults.cc:
    Fix fault formating and code for traps
src/arch/sparc/intregfile.hh:
    allocate the correct number of global registers
src/arch/sparc/isa/decoder.isa:
    fix a couple of bugs in the decoder: wrasi should write asi not ccr, done/retry should get hpstate from htstate
src/arch/sparc/pagetable.hh:
    cleanup/fix page table code
src/arch/sparc/tlb.cc:
    implement more mmaped iprs, fix numbered insertion  code, add function to dump tlb contents
src/arch/sparc/tlb.hh:
    add functions to write TagAccess register on tlb miss and to dump all tlb entries for debugging
src/cpu/exetrace.cc:
    dump tlb entries on error, don't consider differences the cycle we take a trap to be bad.

--HG--
extra : convert_revision : d7d771900f6f25219f3dc6a6e51986d342a32e03

1 files changed, 1 insertions, 1 deletions

diff --git a/src/arch/sparc/intregfile.hh b/src/arch/sparc/intregfile.hh
index 59f767e8e..d66d0fcb7 100644
--- a/src/arch/sparc/intregfile.hh
+++ b/src/arch/sparc/intregfile.hh
@@ -67,7 +67,7 @@ namespace SparcISA
                 (unsigned int)(-1) :
                 (1 << FrameOffsetBits) - 1;
 
-        IntReg regGlobals[MaxGL][RegsPerFrame];
+        IntReg regGlobals[MaxGL+1][RegsPerFrame];
         IntReg regSegments[2 * NWindows][RegsPerFrame];
         IntReg microRegs[NumMicroIntRegs];