Merge zizzer:/bk/newmem

into  zower.eecs.umich.edu:/eecshome/m5/newmem

src/arch/isa_parser.py:
src/arch/sparc/isa/formats/mem/basicmem.isa:
src/arch/sparc/isa/formats/mem/blockmem.isa:
src/arch/sparc/isa/formats/mem/util.isa:
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
src/cpu/o3/iew_impl.hh:
    Hand Merge

--HG--
extra : convert_revision : ae1b25cde85ab8ec275a09d554acd372887d4d47

1 files changed, 8 insertions, 2 deletions

diff --git a/src/arch/sparc/intregfile.hh b/src/arch/sparc/intregfile.hh
index d66d0fcb7..716d45a65 100644
--- a/src/arch/sparc/intregfile.hh
+++ b/src/arch/sparc/intregfile.hh
@@ -34,6 +34,7 @@
 
 #include "arch/sparc/isa_traits.hh"
 #include "arch/sparc/types.hh"
+#include "base/bitfield.hh"
 
 #include <string>
 
@@ -54,15 +55,19 @@ namespace SparcISA
       private:
         friend class RegFile;
       protected:
+        //The number of bits needed to index into each 8 register frame
         static const int FrameOffsetBits = 3;
+        //The number of bits to choose between the 4 sets of 8 registers
         static const int FrameNumBits = 2;
 
+        //The number of registers per "frame" (8)
         static const int RegsPerFrame = 1 << FrameOffsetBits;
-        static const int FrameNumMask =
+        //A mask to get the frame number
+        static const uint64_t FrameNumMask =
                 (FrameNumBits == sizeof(int)) ?
                 (unsigned int)(-1) :
                 (1 << FrameNumBits) - 1;
-        static const int FrameOffsetMask =
+        static const uint64_t FrameOffsetMask =
                 (FrameOffsetBits == sizeof(int)) ?
                 (unsigned int)(-1) :
                 (1 << FrameOffsetBits) - 1;
@@ -70,6 +75,7 @@ namespace SparcISA
         IntReg regGlobals[MaxGL+1][RegsPerFrame];
         IntReg regSegments[2 * NWindows][RegsPerFrame];
         IntReg microRegs[NumMicroIntRegs];
+        IntReg regs[NumIntRegs];
 
         enum regFrame {Globals, Outputs, Locals, Inputs, NumFrames};