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| author | Mitch Hayenga <mitch.hayenga@arm.com> | 2015-09-30 11:14:19 -0500 |
|---|---|---|
| committer | Mitch Hayenga <mitch.hayenga@arm.com> | 2015-09-30 11:14:19 -0500 |
| commit | a5c4eb3de9deb3a71a6a5230a25ff5962e584980 (patch) | |
| tree | 874b659c6a5eaa1316cde9eb82ec7d08badf638a /src/arch/sparc/isa.cc | |
| parent | e255fa053f8d105de8d188077a318124a3aad9ce (diff) | |
| download | gem5-a5c4eb3de9deb3a71a6a5230a25ff5962e584980.tar.xz | |
isa,cpu: Add support for FS SMT Interrupts
Adds per-thread interrupt controllers and thread/context logic
so that interrupts properly get routed in SMT systems.
Diffstat (limited to 'src/arch/sparc/isa.cc')
| -rw-r--r-- | src/arch/sparc/isa.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc index a588eaf66..aa10a0b46 100644 --- a/src/arch/sparc/isa.cc +++ b/src/arch/sparc/isa.cc @@ -591,9 +591,9 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc) { tl = val; if (hpstate.tlz && tl == 0 && !hpstate.hpriv) - tc->getCpuPtr()->postInterrupt(IT_TRAP_LEVEL_ZERO, 0); + tc->getCpuPtr()->postInterrupt(0, IT_TRAP_LEVEL_ZERO, 0); else - tc->getCpuPtr()->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0); + tc->getCpuPtr()->clearInterrupt(0, IT_TRAP_LEVEL_ZERO, 0); return; } case MISCREG_CWP: |