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| author | Gabe Black <gblack@eecs.umich.edu> | 2011-10-09 23:48:27 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2011-10-09 23:48:27 -0700 |
| commit | 5bab52d56ddd482ae7eb1a6ae45d2a97fd457ca2 (patch) | |
| tree | 53445f377a4abb37031138786d3ac9ab1e91d84e /src/arch/sparc/isa.hh | |
| parent | 48b40cff650cb071b189826af2f2e1f78434f49b (diff) | |
| download | gem5-5bab52d56ddd482ae7eb1a6ae45d2a97fd457ca2.tar.xz | |
[mq]: sefssparcregfile.patch
Diffstat (limited to 'src/arch/sparc/isa.hh')
| -rw-r--r-- | src/arch/sparc/isa.hh | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh index f00068bbc..a480630be 100644 --- a/src/arch/sparc/isa.hh +++ b/src/arch/sparc/isa.hh @@ -114,7 +114,6 @@ class ISA // These need to check the int_dis field and if 0 then // set appropriate bit in softint and checkinterrutps on the cpu -#if FULL_SYSTEM void setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc); MiscReg readFSReg(int miscReg, ThreadContext * tc); @@ -138,7 +137,6 @@ class ISA typedef CpuEventWrapper<ISA, &ISA::processHSTickCompare> HSTickCompareEvent; HSTickCompareEvent *hSTickCompare; -#endif static const int NumGlobalRegs = 8; static const int NumWindowedRegs = 24; @@ -205,11 +203,9 @@ class ISA ISA() { -#if FULL_SYSTEM tickCompare = NULL; sTickCompare = NULL; hSTickCompare = NULL; -#endif clear(); } |