SPARC: Fold the MiscRegFile all the way into the ISA object.

1 files changed, 112 insertions, 7 deletions

diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index bba578ef1..c953be01b 100644
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -31,22 +31,131 @@
 #ifndef __ARCH_SPARC_ISA_HH__
 #define __ARCH_SPARC_ISA_HH__
 
-#include "arch/sparc/miscregfile.hh"
+#include "arch/sparc/registers.hh"
 #include "arch/sparc/types.hh"
+#include "config/full_system.hh"
+#include "cpu/cpuevent.hh"
+
+#include <string>
+#include <ostream>
 
 class Checkpoint;
 class EventManager;
+class ThreadContext;
 
 namespace SparcISA
 {
     class ISA
     {
-      protected:
-        MiscRegFile miscRegFile;
+      private:
+
+        /* ASR Registers */
+        //uint64_t y;           // Y (used in obsolete multiplication)
+        //uint8_t ccr;          // Condition Code Register
+        uint8_t asi;            // Address Space Identifier
+        uint64_t tick;          // Hardware clock-tick counter
+        uint8_t fprs;           // Floating-Point Register State
+        uint64_t gsr;           // General Status Register
+        uint64_t softint;
+        uint64_t tick_cmpr;     // Hardware tick compare registers
+        uint64_t stick;         // Hardware clock-tick counter
+        uint64_t stick_cmpr;    // Hardware tick compare registers
+
+
+        /* Privileged Registers */
+        uint64_t tpc[MaxTL];    // Trap Program Counter (value from
+                                // previous trap level)
+        uint64_t tnpc[MaxTL];   // Trap Next Program Counter (value from
+                                // previous trap level)
+        uint64_t tstate[MaxTL]; // Trap State
+        uint16_t tt[MaxTL];     // Trap Type (Type of trap which occured
+                                // on the previous level)
+        uint64_t tba;           // Trap Base Address
+
+        uint16_t pstate;        // Process State Register
+        uint8_t tl;             // Trap Level
+        uint8_t pil;            // Process Interrupt Register
+        uint8_t cwp;            // Current Window Pointer
+        //uint8_t cansave;      // Savable windows
+        //uint8_t canrestore;   // Restorable windows
+        //uint8_t cleanwin;     // Clean windows
+        //uint8_t otherwin;     // Other windows
+        //uint8_t wstate;               // Window State
+        uint8_t gl;             // Global level register
+
+        /** Hyperprivileged Registers */
+        uint64_t hpstate;       // Hyperprivileged State Register
+        uint64_t htstate[MaxTL];// Hyperprivileged Trap State Register
+        uint64_t hintp;
+        uint64_t htba;          // Hyperprivileged Trap Base Address register
+        uint64_t hstick_cmpr;   // Hardware tick compare registers
+
+        uint64_t strandStatusReg;// Per strand status register
+
+        /** Floating point misc registers. */
+        uint64_t fsr;           // Floating-Point State Register
+
+        /** MMU Internal Registers */
+        uint16_t priContext;
+        uint16_t secContext;
+        uint16_t partId;
+        uint64_t lsuCtrlReg;
+
+        uint64_t scratchPad[8];
+
+        uint64_t cpu_mondo_head;
+        uint64_t cpu_mondo_tail;
+        uint64_t dev_mondo_head;
+        uint64_t dev_mondo_tail;
+        uint64_t res_error_head;
+        uint64_t res_error_tail;
+        uint64_t nres_error_head;
+        uint64_t nres_error_tail;
+
+        // These need to check the int_dis field and if 0 then
+        // set appropriate bit in softint and checkinterrutps on the cpu
+#if FULL_SYSTEM
+        void  setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc);
+        MiscReg readFSReg(int miscReg, ThreadContext * tc);
+
+        // Update interrupt state on softint or pil change
+        void checkSoftInt(ThreadContext *tc);
+
+        /** Process a tick compare event and generate an interrupt on the cpu if
+         * appropriate. */
+        void processTickCompare(ThreadContext *tc);
+        void processSTickCompare(ThreadContext *tc);
+        void processHSTickCompare(ThreadContext *tc);
 
+        typedef CpuEventWrapper<ISA,
+                &ISA::processTickCompare> TickCompareEvent;
+        TickCompareEvent *tickCompare;
+
+        typedef CpuEventWrapper<ISA,
+                &ISA::processSTickCompare> STickCompareEvent;
+        STickCompareEvent *sTickCompare;
+
+        typedef CpuEventWrapper<ISA,
+                &ISA::processHSTickCompare> HSTickCompareEvent;
+        HSTickCompareEvent *hSTickCompare;
+#endif
       public:
+
         void clear();
 
+        void serialize(EventManager *em, std::ostream & os);
+
+        void unserialize(EventManager *em, Checkpoint *cp,
+                         const std::string & section);
+
+      protected:
+
+        bool isHyperPriv() { return (hpstate & (1 << 2)); }
+        bool isPriv() { return (hpstate & (1 << 2)) || (pstate & (1 << 2)); }
+        bool isNonPriv() { return !isPriv(); }
+
+      public:
+
         MiscReg readMiscRegNoEffect(int miscReg);
         MiscReg readMiscReg(int miscReg, ThreadContext *tc);
 
@@ -62,10 +171,6 @@ namespace SparcISA
             return reg;
         }
 
-        void serialize(EventManager *em, std::ostream &os);
-        void unserialize(EventManager *em, Checkpoint *cp,
-                const std::string &section);
-
         ISA()
         {
             clear();