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author | Ali Saidi <saidi@eecs.umich.edu> | 2007-02-24 22:05:01 -0500 |
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committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-02-24 22:05:01 -0500 |
commit | cf0e202cbad9823bdd3361164f4b2ee41c4c1501 (patch) | |
tree | 2aaf194ba788e1a370970c8bb1e4c80f29d8cee6 /src/arch/sparc/isa/decoder.isa | |
parent | f01f8f1be6a536580371428aa3e8e654d97fb868 (diff) | |
download | gem5-cf0e202cbad9823bdd3361164f4b2ee41c4c1501.tar.xz |
make m5 readfile work on solaris... we can have a solaris regression soon!
src/arch/sparc/isa/decoder.isa:
add readfile and break to sparc decoder
src/arch/sparc/isa/operands.isa:
fix O0-O5 operands registers
util/m5/Makefile.sparc:
Make sparc makefile compile a 64bit binary
util/m5/m5.c:
readfile was in here twice, once will be sufficient I think
util/m5/m5op_sparc.S:
implement readfile and debugbreak
--HG--
extra : convert_revision : 139b3f480ee6342b37b5642e072c8486d91a3944
Diffstat (limited to 'src/arch/sparc/isa/decoder.isa')
-rw-r--r-- | src/arch/sparc/isa/decoder.isa | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index e2d1707dd..c07295248 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -1014,6 +1014,11 @@ decode OP default Unknown::unknown() // we have 7 bits of space here to play with... 0x21: m5exit({{PseudoInst::m5exit(xc->tcBase(), O0); }}, No_OpClass, IsNonSpeculative); + 0x50: m5readfile({{ + O0 = PseudoInst::readfile(xc->tcBase(), O0, O1, O2); + }}, IsNonSpeculative); + 0x51: m5break({{PseudoInst::debugbreak(xc->tcBase()); + }}, IsNonSpeculative); 0x54: m5panic({{ panic("M5 panic instruction called at pc=%#x.", xc->readPC()); }}, No_OpClass, IsNonSpeculative); |