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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-02-25 10:16:04 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-02-25 10:16:04 -0800 |
| commit | 15940d06b5f6aabbe917a2a8c4cc4bb1cab991e2 (patch) | |
| tree | 1d03fcd57fea0d42cf4f718da19fba69d2d15eeb /src/arch/sparc/isa/decoder.isa | |
| parent | 1b336a8fe713dad2e77c5f973d9eb2f5fbcfb585 (diff) | |
| download | gem5-15940d06b5f6aabbe917a2a8c4cc4bb1cab991e2.tar.xz | |
SPARC: Adjust a few instructions to not write registers in initiateAcc.
Diffstat (limited to 'src/arch/sparc/isa/decoder.isa')
| -rw-r--r-- | src/arch/sparc/isa/decoder.isa | 18 |
1 files changed, 8 insertions, 10 deletions
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index c35b231ff..e34ca033f 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -1231,16 +1231,14 @@ decode OP default Unknown::unknown() 0x23: Load::lddf({{Frd.udw = Mem.udw;}}); 0x24: Store::stf({{Mem.uw = Frds.uw;}}); 0x25: decode RD { - 0x0: Store::stfsr({{fault = checkFpEnableFault(xc); - if (fault) - return fault; - Mem.uw = Fsr<31:0>; - Fsr = insertBits(Fsr,16,14,0);}}); - 0x1: Store::stxfsr({{fault = checkFpEnableFault(xc); - if (fault) - return fault; - Mem.udw = Fsr; - Fsr = insertBits(Fsr,16,14,0);}}); + 0x0: StoreFsr::stfsr({{fault = checkFpEnableFault(xc); + if (fault) + return fault; + Mem.uw = Fsr<31:0>;}}); + 0x1: StoreFsr::stxfsr({{fault = checkFpEnableFault(xc); + if (fault) + return fault; + Mem.udw = Fsr;}}); default: FailUnimpl::stfsrOther(); } 0x26: stqf({{fault = new FpDisabled;}}); |