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| author | Korey Sewell <ksewell@umich.edu> | 2011-06-09 01:34:06 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2011-06-09 01:34:06 -0400 |
| commit | 1a451cd2c5ec20c27c39a1cd3e3b5422c2b4f679 (patch) | |
| tree | bcd4c037bb4f6822d5b1e3112ebca7060e3dbcae /src/arch/sparc/isa/decoder.isa | |
| parent | 67bb3070032fcb944a63aabb4ecfff692840e7bf (diff) | |
| download | gem5-1a451cd2c5ec20c27c39a1cd3e3b5422c2b4f679.tar.xz | |
sparc: compilation fixes for inorder
Add a few constants and functions that the InOrder model wants for SPARC.
* * *
sparc: add eaComp function
InOrder separates the address generation from the actual access so give
Sparc that functionality
* * *
sparc: add control flags for branches
branch predictors and other cpu model functions need to know specific information
about branches, so add the necessary flags here
Diffstat (limited to 'src/arch/sparc/isa/decoder.isa')
| -rw-r--r-- | src/arch/sparc/isa/decoder.isa | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index 5ca015a8f..d15d1eb2b 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -141,7 +141,7 @@ decode OP default Unknown::unknown() IntReg midVal; R15 = midVal = (Pstate<3:> ? (PC)<31:0> : PC); NNPC = midVal + disp; - }}); + }},None, None, IsIndirectControl, IsCall); 0x2: decode OP3 { format IntOp { 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}}); @@ -1005,7 +1005,7 @@ decode OP default Unknown::unknown() Rd = PC; NNPC = target; } - }}); + }}, IsUncondControl, IsIndirectControl); 0x39: Branch::return({{ Addr target = Rs1 + Rs2_or_imm13; if (fault == NoFault) { @@ -1025,7 +1025,7 @@ decode OP default Unknown::unknown() Canrestore = Canrestore - 1; } } - }}); + }}, IsUncondControl, IsIndirectControl, IsReturn); 0x3A: decode CC { 0x0: Trap::tcci({{ |