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author | Ali Saidi <saidi@eecs.umich.edu> | 2006-12-09 18:00:40 -0500 |
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committer | Ali Saidi <saidi@eecs.umich.edu> | 2006-12-09 18:00:40 -0500 |
commit | 81a00fdcfef4ecffd57a909db67ca0ff3b99de3a (patch) | |
tree | a80cc38ae0827b41f66560750606bb9061955481 /src/arch/sparc/isa/decoder.isa | |
parent | ed22eb781dc7714c1b2ca17cf17824917e38319c (diff) | |
download | gem5-81a00fdcfef4ecffd57a909db67ca0ff3b99de3a.tar.xz |
Allocate the correct number of global registers
Fix fault formating and code for traps
fix a couple of bugs in the decoder
Cleanup/fix page table entry code
Implement more mmaped iprs, fix numbered tlb insertion code, add function to dump tlb contents
Don't panic if we differ from legion on a tcc instruction because of where legion prints its data and where we print our data
src/arch/sparc/faults.cc:
Fix fault formating and code for traps
src/arch/sparc/intregfile.hh:
allocate the correct number of global registers
src/arch/sparc/isa/decoder.isa:
fix a couple of bugs in the decoder: wrasi should write asi not ccr, done/retry should get hpstate from htstate
src/arch/sparc/pagetable.hh:
cleanup/fix page table code
src/arch/sparc/tlb.cc:
implement more mmaped iprs, fix numbered insertion code, add function to dump tlb contents
src/arch/sparc/tlb.hh:
add functions to write TagAccess register on tlb miss and to dump all tlb entries for debugging
src/cpu/exetrace.cc:
dump tlb entries on error, don't consider differences the cycle we take a trap to be bad.
--HG--
extra : convert_revision : d7d771900f6f25219f3dc6a6e51986d342a32e03
Diffstat (limited to 'src/arch/sparc/isa/decoder.isa')
-rw-r--r-- | src/arch/sparc/isa/decoder.isa | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index b893797b0..7a48042c2 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -526,7 +526,7 @@ decode OP default Unknown::unknown() 0x00: NoPriv::wry({{Y = Rs1 ^ Rs2_or_imm13;}}); //0x01 should cause an illegal instruction exception 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}}); - 0x03: NoPriv::wrasi({{Ccr = Rs1 ^ Rs2_or_imm13;}}); + 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}}); //0x04-0x05 should cause an illegal instruction exception 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}}); //0x07-0x0E should cause an illegal instruction exception @@ -1017,6 +1017,7 @@ decode OP default Unknown::unknown() Asi = Tstate<31:24>; Ccr = Tstate<39:32>; Gl = Tstate<42:40>; + Hpstate = Htstate; NPC = Tpc; NNPC = Tnpc; Tl = Tl - 1; |