more fp fixes

fix unaligned accesses in mmaped disk device

src/arch/sparc/isa/decoder.isa:
    get (ld|st)fsr ops working right. In reality the fp enable check needs to go higher up in the emitted code
src/arch/sparc/isa/formats/basic.isa:
    move the cexec into the aexec field
src/cpu/exetrace.cc:
    copy the exception state from legion when we get it wrong. We aren't going to get it right without an fp emulation layer
src/dev/sparc/mm_disk.cc:
src/dev/sparc/mm_disk.hh:
    fix unaligned accesses in the memory mapped disk device

--HG--
extra : convert_revision : aaa33096b08cf0563fe291d984a87493a117e528

1 files changed, 17 insertions, 7 deletions

diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index e56e9d81d..fb606c7cc 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -807,14 +807,12 @@ decode OP default Unknown::unknown()
                             float t = Frds.sw;
                             if (t != Frs2s.sf)
                                Fsr = insertBits(Fsr, 4,0, 0x01);
-                            Fsr |= Fsr<4:0> << 5;
                     }});
                     0xD2: fdtoi({{
                             Frds.sw = static_cast<int32_t>(Frs2.df);
                             double t = Frds.sw;
                             if (t != Frs2.df)
                                Fsr = insertBits(Fsr, 4,0, 0x01);
-                            Fsr |= Fsr<4:0> << 5;
                     }});
                     0xD3: FpUnimpl::fqtoi();
                     default: FailUnimpl::fpop1();
@@ -1245,18 +1243,30 @@ decode OP default Unknown::unknown()
         format Trap {
             0x20: Load::ldf({{Frds.uw = Mem.uw;}});
             0x21: decode RD {
-                0x0: Load::ldfsr({{Fsr = Mem.uw | Fsr<63:32>;}});
-                0x1: Load::ldxfsr({{Fsr = Mem.udw;}});
+                0x0: Load::ldfsr({{fault = checkFpEnableFault(xc);
+                                     if (fault)
+                                         return fault;
+                                   Fsr = Mem.uw | Fsr<63:32>;}});
+                0x1: Load::ldxfsr({{fault = checkFpEnableFault(xc);
+                                     if (fault)
+                                         return fault;
+                                    Fsr = Mem.udw;}});
                 default: FailUnimpl::ldfsrOther();
             }
             0x22: ldqf({{fault = new FpDisabled;}});
             0x23: Load::lddf({{Frd.udw = Mem.udw;}});
             0x24: Store::stf({{Mem.uw = Frds.uw;}});
             0x25: decode RD {
-                0x0: Store::stfsr({{Mem.uw = Fsr<31:0>;
-                                    Fsr = insertBits(Fsr,16,14,0);}});
-                0x1: Store::stxfsr({{Mem.udw = Fsr;
+                0x0: Store::stfsr({{fault = checkFpEnableFault(xc);
+                                     if (fault)
+                                         return fault;
+                                    Mem.uw = Fsr<31:0>;
                                     Fsr = insertBits(Fsr,16,14,0);}});
+                0x1: Store::stxfsr({{fault = checkFpEnableFault(xc);
+                                     if (fault)
+                                         return fault;
+                                     Mem.udw = Fsr;
+                                     Fsr = insertBits(Fsr,16,14,0);}});
                 default: FailUnimpl::stfsrOther();
             }
             0x26: stqf({{fault = new FpDisabled;}});