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authorAli Saidi <saidi@eecs.umich.edu>2007-02-02 19:02:27 -0500
committerAli Saidi <saidi@eecs.umich.edu>2007-02-02 19:02:27 -0500
commitecef27f172523503eb64fc7b2d5e82c2f83b5210 (patch)
treef3bdd7d8144a35abb4472ce570e9432f5c4765be /src/arch/sparc/isa/decoder.isa
parent665ddde57a2f6de6cafd5046f3ee00297e992ce0 (diff)
downloadgem5-ecef27f172523503eb64fc7b2d5e82c2f83b5210.tar.xz
more sparc fixes
src/arch/sparc/isa/decoder.isa: fix rdgsr fault check src/arch/sparc/tlb.cc: block asis are now supported --HG-- extra : convert_revision : cf55d648d2c5184fab03b6fe057d0e33c1dfc393
Diffstat (limited to 'src/arch/sparc/isa/decoder.isa')
-rw-r--r--src/arch/sparc/isa/decoder.isa8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index 57e0857f1..e56e9d81d 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -479,10 +479,10 @@ decode OP default Unknown::unknown()
0x11: PrivCheck::rdpic({{Rd = Pic;}}, {{Pcr<0:>}});
//0x12 should cause an illegal instruction exception
0x13: NoPriv::rdgsr({{
- if(Fprs<2:> == 0 || Pstate<4:> == 0)
- Rd = Gsr;
- else
- fault = new FpDisabled;
+ fault = checkFpEnableFault(xc);
+ if (fault)
+ return fault;
+ Rd = Gsr;
}});
//0x14-0x15 should cause an illegal instruction exception
0x16: Priv::rdsoftint({{Rd = Softint;}});