Bring casa and casxa up to date

src/arch/sparc/isa/decoder.isa:
    Fix up the casa and casxa instructions.
src/arch/sparc/isa/formats/formats.isa:
    This is handled in loadstore.isa now
src/arch/sparc/isa/formats/mem/basicmem.isa:
src/arch/sparc/isa/formats/mem/blockmem.isa:
    Renamed doSplitExecute to doDualSplitExecute. This differentiates between the version that does both a register and immediate version, and one that just does a register version.
src/arch/sparc/isa/formats/mem/mem.isa:
    The cas format is handled in loadstore.isa as well now.
src/arch/sparc/isa/formats/mem/util.isa:
    Reorganized things a bit to better support cas

--HG--
extra : convert_revision : 12411e89e763287e52f9825bf7a417b263c1037f

1 files changed, 12 insertions, 10 deletions

diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index aa3b6de6f..a64ff09bb 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -1072,19 +1072,21 @@ decode OP default Unknown::unknown()
                         {{fault = new DataAccessException;}});
                 }
             }
-            0x3C: Cas::casa({{
-                uint64_t val = Mem.uw;
-                if(Rs2.uw == val)
+            0x3C: Cas::casa(
+                {{uReg0 = Mem.uw;}},
+                {{if(Rs2.uw == uReg0)
                         Mem.uw = Rd.uw;
-                Rd.uw = val;
-            }});
+                else
+                        storeCond = false;
+                Rd.uw = uReg0;}});
             0x3D: Nop::prefetcha({{ }});
-            0x3E: Cas::casxa({{
-                uint64_t val = Mem.udw;
-                if(Rs2 == val)
+            0x3E: Cas::casxa(
+                {{uReg0 = Mem.udw;}},
+                {{if(Rs2 == uReg0)
                         Mem.udw = Rd;
-                Rd = val;
-            }});
+                else
+                        storeCond = false;
+                Rd = uReg0;}});
         }
     }
 }