diff options
author | Gabe Black <gblack@eecs.umich.edu> | 2007-09-25 20:11:03 -0700 |
---|---|---|
committer | Gabe Black <gblack@eecs.umich.edu> | 2007-09-25 20:11:03 -0700 |
commit | 25a9b6ea5e232590240a7ffc6ff769ffdfdc1e04 (patch) | |
tree | 109682f8fe9e6f24616ba2a4db303eeb890151cd /src/arch/sparc/isa/decoder.isa | |
parent | e735001d5463b30dacf997bfb2578c433db98154 (diff) | |
download | gem5-25a9b6ea5e232590240a7ffc6ff769ffdfdc1e04.tar.xz |
SPARC: Remove parameter that was only ever set to one value.
--HG--
extra : convert_revision : 3c22e576d95bdc7566bbce9b92cf2a6ff153a66f
Diffstat (limited to 'src/arch/sparc/isa/decoder.isa')
-rw-r--r-- | src/arch/sparc/isa/decoder.isa | 69 |
1 files changed, 34 insertions, 35 deletions
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index eaeba3e2d..c35b231ff 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -1116,76 +1116,75 @@ decode OP default Unknown::unknown() Rd.uw = tmp; }}, MEM_SWAP); format LoadAlt { - 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}}); - 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}}); - 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}}); + 0x10: lduwa({{Rd = Mem.uw;}}); + 0x11: lduba({{Rd = Mem.ub;}}); + 0x12: lduha({{Rd = Mem.uhw;}}); 0x13: decode EXT_ASI { //ASI_LDTD_AIUP 0x22: TwinLoad::ldtx_aiup( {{RdLow.udw = (Mem.tudw).a; - RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); + RdHigh.udw = (Mem.tudw).b;}}); //ASI_LDTD_AIUS 0x23: TwinLoad::ldtx_aius( {{RdLow.udw = (Mem.tudw).a; - RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); + RdHigh.udw = (Mem.tudw).b;}}); //ASI_QUAD_LDD 0x24: TwinLoad::ldtx_quad_ldd( {{RdLow.udw = (Mem.tudw).a; - RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); + RdHigh.udw = (Mem.tudw).b;}}); //ASI_LDTX_REAL 0x26: TwinLoad::ldtx_real( {{RdLow.udw = (Mem.tudw).a; - RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); + RdHigh.udw = (Mem.tudw).b;}}); //ASI_LDTX_N 0x27: TwinLoad::ldtx_n( {{RdLow.udw = (Mem.tudw).a; - RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); + RdHigh.udw = (Mem.tudw).b;}}); //ASI_LDTX_AIUP_L 0x2A: TwinLoad::ldtx_aiup_l( {{RdLow.udw = (Mem.tudw).a; - RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); + RdHigh.udw = (Mem.tudw).b;}}); //ASI_LDTX_AIUS_L 0x2B: TwinLoad::ldtx_aius_l( {{RdLow.udw = (Mem.tudw).a; - RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); + RdHigh.udw = (Mem.tudw).b;}}); //ASI_LDTX_L 0x2C: TwinLoad::ldtx_l( {{RdLow.udw = (Mem.tudw).a; - RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); + RdHigh.udw = (Mem.tudw).b;}}); //ASI_LDTX_REAL_L 0x2E: TwinLoad::ldtx_real_l( {{RdLow.udw = (Mem.tudw).a; - RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); + RdHigh.udw = (Mem.tudw).b;}}); //ASI_LDTX_N_L 0x2F: TwinLoad::ldtx_n_l( {{RdLow.udw = (Mem.tudw).a; - RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); + RdHigh.udw = (Mem.tudw).b;}}); //ASI_LDTX_P 0xE2: TwinLoad::ldtx_p( {{RdLow.udw = (Mem.tudw).a; - RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); + RdHigh.udw = (Mem.tudw).b;}}); //ASI_LDTX_S 0xE3: TwinLoad::ldtx_s( {{RdLow.udw = (Mem.tudw).a; - RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); + RdHigh.udw = (Mem.tudw).b;}}); //ASI_LDTX_PL 0xEA: TwinLoad::ldtx_pl( {{RdLow.udw = (Mem.tudw).a; - RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); + RdHigh.udw = (Mem.tudw).b;}}); //ASI_LDTX_SL 0xEB: TwinLoad::ldtx_sl( {{RdLow.udw = (Mem.tudw).a; - RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); + RdHigh.udw = (Mem.tudw).b;}}); default: ldtwa({{ RdLow = (Mem.tuw).a; - RdHigh = (Mem.tuw).b; - }}, {{EXT_ASI}}); + RdHigh = (Mem.tuw).b;}}); } } format StoreAlt { - 0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}}); - 0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}}); - 0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}}); + 0x14: stwa({{Mem.uw = Rd;}}); + 0x15: stba({{Mem.ub = Rd;}}); + 0x16: stha({{Mem.uhw = Rd;}}); 0x17: sttwa({{ //This temporary needs to be here so that the parser //will correctly identify this instruction as a store. @@ -1195,25 +1194,25 @@ decode OP default Unknown::unknown() temp.a = RdLow<31:0>; temp.b = RdHigh<31:0>; Mem.tuw = temp; - }}, {{EXT_ASI}}); + }}); } format LoadAlt { - 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}}); - 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}, {{EXT_ASI}}); - 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}, {{EXT_ASI}}); - 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}}); + 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}); + 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}); + 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}); + 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}); } 0x1D: SwapAlt::ldstuba({{Mem.ub = 0xFF;}}, {{ uint8_t tmp = mem_data; Rd.ub = tmp; - }}, {{EXT_ASI}}, MEM_SWAP); - 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}, {{EXT_ASI}}); + }}, MEM_SWAP); + 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}); 0x1F: SwapAlt::swapa({{Mem.uw = Rd.uw}}, {{ uint32_t tmp = mem_data; Rd.uw = tmp; - }}, {{EXT_ASI}}, MEM_SWAP); + }}, MEM_SWAP); format Trap { 0x20: Load::ldf({{Frds.uw = Mem.uw;}}); @@ -1247,7 +1246,7 @@ decode OP default Unknown::unknown() 0x26: stqf({{fault = new FpDisabled;}}); 0x27: Store::stdf({{Mem.udw = Frd.udw;}}); 0x2D: Nop::prefetch({{ }}); - 0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}}, {{EXT_ASI}}); + 0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}}); 0x32: ldqfa({{fault = new FpDisabled;}}); format LoadAlt { 0x33: decode EXT_ASI { @@ -1299,7 +1298,7 @@ decode OP default Unknown::unknown() //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 0x1F: FailUnimpl::ldblockf_aiusl(); //ASI_BLOCK_PRIMARY - 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}, {{EXT_ASI}}); + 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}); //ASI_BLOCK_SECONDARY 0xF1: FailUnimpl::ldblockf_s(); //ASI_BLOCK_PRIMARY_LITTLE @@ -1382,7 +1381,7 @@ decode OP default Unknown::unknown() //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 0x1F: FailUnimpl::stblockf_aiusl(); //ASI_BLOCK_PRIMARY - 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}, {{EXT_ASI}}); + 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}); //ASI_BLOCK_SECONDARY 0xF1: FailUnimpl::stblockf_s(); //ASI_BLOCK_PRIMARY_LITTLE @@ -1419,11 +1418,11 @@ decode OP default Unknown::unknown() {{ uint32_t tmp = mem_data; Rd.uw = tmp; - }}, {{EXT_ASI}}, MEM_SWAP_COND); + }}, MEM_SWAP_COND); 0x3D: Nop::prefetcha({{ }}); 0x3E: CasAlt::casxa({{mem_data = gtoh(Rs2); Mem.udw = Rd.udw; }}, - {{ Rd.udw = mem_data; }}, {{EXT_ASI}}, MEM_SWAP_COND); + {{ Rd.udw = mem_data; }}, MEM_SWAP_COND); } } } |