make ldtw(a) -- Twin 32 bit load work correctly -- by doing it the same way as the twin 64 bit loads

src/arch/isa_parser.py:
src/arch/sparc/isa/decoder.isa:
src/arch/sparc/isa/operands.isa:
src/base/bigint.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
src/mem/packet_access.hh:
    make ldtw(a) Twin 32 bit load work correctly

--HG--
extra : convert_revision : 2646b269d58cc1774e896065875a56cf5e313b42

1 files changed, 4 insertions, 6 deletions

diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index 36b9d1caa..2e85e1274 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -1160,9 +1160,8 @@ decode OP default Unknown::unknown()
             0x01: ldub({{Rd = Mem.ub;}});
             0x02: lduh({{Rd = Mem.uhw;}});
             0x03: ldtw({{
-                uint64_t val = Mem.udw;
-                RdLow = val<31:0>;
-                RdHigh = val<63:32>;
+                        RdLow = (Mem.tuw).a;
+                        RdHigh = (Mem.tuw).b;
             }});
         }
         format Store {
@@ -1250,9 +1249,8 @@ decode OP default Unknown::unknown()
                     {{RdLow.udw = (Mem.tudw).a;
                       RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
                 default: ldtwa({{
-                        uint64_t val = Mem.udw;
-                        RdLow = val<31:0>;
-                        RdHigh = val<63:32>;
+                        RdLow = (Mem.tuw).a;
+                        RdHigh = (Mem.tuw).b;
                         }}, {{EXT_ASI}});
             }
         }