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| author | Ali Saidi <saidi@eecs.umich.edu> | 2007-01-10 22:19:13 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-01-10 22:19:13 -0500 |
| commit | 9d04510869fe66d59a168660925a8387c0fba1b8 (patch) | |
| tree | 62625bd13f32c4107ed3f24df65421e5fe086232 /src/arch/sparc/isa/decoder.isa | |
| parent | 28a83c6d1c2673448aaedfb0eb131d6c6604badf (diff) | |
| download | gem5-9d04510869fe66d59a168660925a8387c0fba1b8.tar.xz | |
bug fixes to get us to 145m instructions
src/arch/sparc/intregfile.cc:
some checks to make sure that the cwp and global register flattening stuff is working. These things have caught a couple of bugs so I think it would be good to keep them around at least for now
src/arch/sparc/isa/decoder.isa:
fix smul instruction to write Y correctly
src/arch/sparc/miscregfile.cc:
legion always returns du and dl set, so we need to emulate that for now at least
--HG--
extra : convert_revision : 82f9276340888f1e43071c69504486efdcfdb3a8
Diffstat (limited to 'src/arch/sparc/isa/decoder.isa')
| -rw-r--r-- | src/arch/sparc/isa/decoder.isa | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index e2bebd987..2e1344a8f 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -1,4 +1,4 @@ -// Copyright (c) 2006 The Regents of The University of Michigan +// Copyright (c) 2006-2007 The Regents of The University of Michigan // All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -184,7 +184,7 @@ decode OP default Unknown::unknown() }}); 0x0B: smul({{ Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>; - Y = Rd.sdw; + Y = Rd.sdw<63:32>; }}); 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}}); 0x0D: udivx({{ |