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| author | Gabe Black <gblack@eecs.umich.edu> | 2006-12-16 12:55:15 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-12-16 12:55:15 -0500 |
| commit | c9f18981f9283095548c37aea6e7b2db648b70b0 (patch) | |
| tree | a6141c7e385f979673f1a1d380262cb3ab0f7572 /src/arch/sparc/isa/decoder.isa | |
| parent | 385a3ff05433fcc4eca032505d0ce1bb2ca7201c (diff) | |
| parent | b9d069167cc4700495a5ccaf938093731208dca8 (diff) | |
| download | gem5-c9f18981f9283095548c37aea6e7b2db648b70b0.tar.xz | |
Merge zizzer:/bk/sparcfs/
into zower.eecs.umich.edu:/eecshome/m5/sparcfs
--HG--
extra : convert_revision : 2764b356ef01d1fcb6ed272e4ef96179cd651d4e
Diffstat (limited to 'src/arch/sparc/isa/decoder.isa')
| -rw-r--r-- | src/arch/sparc/isa/decoder.isa | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index 7a48042c2..01fe32ef7 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -1030,7 +1030,7 @@ decode OP default Unknown::unknown() 0x00: lduw({{Rd = Mem.uw;}}); 0x01: ldub({{Rd = Mem.ub;}}); 0x02: lduh({{Rd = Mem.uhw;}}); - 0x03: ldd({{ + 0x03: ldtw({{ uint64_t val = Mem.udw; RdLow = val<31:0>; RdHigh = val<63:32>; @@ -1040,7 +1040,7 @@ decode OP default Unknown::unknown() 0x04: stw({{Mem.uw = Rd.sw;}}); 0x05: stb({{Mem.ub = Rd.sb;}}); 0x06: sth({{Mem.uhw = Rd.shw;}}); - 0x07: std({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}}); + 0x07: sttw({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}}); } format Load { 0x08: ldsw({{Rd = (int32_t)Mem.sw;}}); @@ -1060,7 +1060,7 @@ decode OP default Unknown::unknown() 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}}); 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}}); 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}}); - 0x13: ldda({{ + 0x13: ldtwa({{ uint64_t val = Mem.udw; RdLow = val<31:0>; RdHigh = val<63:32>; @@ -1070,7 +1070,7 @@ decode OP default Unknown::unknown() 0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}}); 0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}}); 0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}}); - 0x17: stda({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{EXT_ASI}}); + 0x17: sttwa({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{EXT_ASI}}); } format LoadAlt { 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}}); |