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author | Gabe Black <gblack@eecs.umich.edu> | 2007-06-12 17:19:14 +0000 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2007-06-12 17:19:14 +0000 |
commit | 02732929e8a69fcdda523ebc7aa511d4cdbb0f0e (patch) | |
tree | 0c4f8c8327b69c0191da08d8ca8ee24b20f37e19 /src/arch/sparc/isa/formats/mem/blockmem.isa | |
parent | 1a3e668446e4b2d2c61651c9ae58e643c2aa3ad2 (diff) | |
parent | 0d8d3f988f835e58e5e53b6ee2be871e7bff9132 (diff) | |
download | gem5-02732929e8a69fcdda523ebc7aa511d4cdbb0f0e.tar.xz |
Merge zizzer.eecs.umich.edu:/bk/newmem
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
--HG--
extra : convert_revision : 1d2efac895a1c8328026a079e0b319a436325616
Diffstat (limited to 'src/arch/sparc/isa/formats/mem/blockmem.isa')
-rw-r--r-- | src/arch/sparc/isa/formats/mem/blockmem.isa | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa b/src/arch/sparc/isa/formats/mem/blockmem.isa index e19016bd0..caf5bb8ce 100644 --- a/src/arch/sparc/isa/formats/mem/blockmem.isa +++ b/src/arch/sparc/isa/formats/mem/blockmem.isa @@ -248,14 +248,14 @@ def template BlockMemConstructor {{ : %(base_class)s("%(mnemonic)s", machInst) { %(constructor)s; - microOps[0] = new %(class_name)s_0(machInst); - microOps[1] = new %(class_name)s_1(machInst); - microOps[2] = new %(class_name)s_2(machInst); - microOps[3] = new %(class_name)s_3(machInst); - microOps[4] = new %(class_name)s_4(machInst); - microOps[5] = new %(class_name)s_5(machInst); - microOps[6] = new %(class_name)s_6(machInst); - microOps[7] = new %(class_name)s_7(machInst); + microops[0] = new %(class_name)s_0(machInst); + microops[1] = new %(class_name)s_1(machInst); + microops[2] = new %(class_name)s_2(machInst); + microops[3] = new %(class_name)s_3(machInst); + microops[4] = new %(class_name)s_4(machInst); + microops[5] = new %(class_name)s_5(machInst); + microops[6] = new %(class_name)s_6(machInst); + microops[7] = new %(class_name)s_7(machInst); } }}; @@ -289,9 +289,9 @@ let {{ for microPc in range(8): flag_code = '' if (microPc == 7): - flag_code = "flags[IsLastMicroOp] = true;" + flag_code = "flags[IsLastMicroop] = true;" elif (microPc == 0): - flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroOp] = true;" + flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroop] = true;" else: flag_code = "flags[IsDelayedCommit] = true;" pcedCode = matcher.sub("Frd_%d" % microPc, code) |